Oxide Semiconductor Bottom-Gate Transistor Layout for Impact Resistance
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Solution Overview
Problem
Semiconductor devices with varied shapes require enhanced impact resistance to withstand external forces effectively, particularly in applications where flexibility and reliability are crucial.
Innovation Solution
A semiconductor device structure incorporating a bottom-gate transistor with a gate electrode layer, gate insulating layer, oxide semiconductor layer, insulating layer, and conductive layer, where the insulating layer and gate insulating layer align end-to-end over the gate electrode layer, and the conductive layer covers the channel formation region, providing comprehensive protection against external impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a conventional transistor structure is used, then the device can be manufactured with standard processes, but the impact resistance is insufficient for flexible applications
Solution Approach 1:
The transistor is divided into distinct functional layers including gate electrode layer, gate insulating layer, oxide semiconductor layer, insulating layer, and conductive layer. Each layer is independently formed and optimized, allowing the structure to be segmented for better impact resistance while maintaining manufacturability through standard thin-film deposition processes
Solution Approach 2:
The transistor employs a composite structure combining multiple materials with different properties: metal oxide semiconductor layer for channel formation, insulating layers for electrical isolation, and conductive layers for electrode functions. This composite approach enhances overall device robustness and impact resistance while maintaining electrical performance
2Reliability
If the insulating layer and gate insulating layer are aligned end-to-end, then comprehensive protection against external impacts is achieved, but the manufacturing precision requirements increase
Solution Approach 1:
The gate insulating layer is formed first as a base layer, followed by the oxide semiconductor layer and insulating layer that are subsequently aligned to it. This preliminary formation of the gate insulating layer provides a reference structure that simplifies subsequent alignment operations and ensures comprehensive protection coverage
Solution Approach 2:
The gate insulating layer serves as an intermediary structure that facilitates alignment between the underlying gate electrode and the upper insulating layer. This intermediate layer acts as a mechanical and electrical buffer, enabling precise alignment while providing comprehensive protection against external impacts
3Ease of operation
If the conductive layer covers the channel formation region and aligns with the gate electrode layer, then the transistor functionality is optimized, but the device complexity increases
Solution Approach 1:
The conductive layer serves multiple functions: it forms the source and drain electrodes, provides electrical connection to the gate electrode layer, and defines the channel formation region boundaries. This multi-functionality optimizes transistor operation while avoiding the need for separate structural elements, thereby limiting the increase in device complexity
Data Source
AI summary
A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.