Oxide Semiconductor Transistor Insulating Stack for Lower On-Resistance
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Solution Overview
Problem
Existing semiconductor devices face increased on-resistance due to etching damage and contact resistance issues during the manufacturing process, particularly in the formation of oxide semiconductor transistors, which affects their performance and efficiency.
Innovation Solution
Incorporating a protective insulating layer with a different chemical composition or density between the gate insulating layer and the lower insulating layer, which reduces etching damage and enhances the contact area between electrodes and the oxide semiconductor layer, thereby decreasing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etching process is used to form oxide semiconductor transistor, then transistor structure is formed, but etching damage increases on-resistance
Solution Approach 1:
A protective insulating layer is introduced as an intermediary between the lower electrode and the gate insulating layer. This protective layer serves as a mediator that prevents direct contact between the etching process and the lower electrode, thereby reducing etching damage and subsequent on-resistance while still allowing the transistor structure to be formed through the gate insulating layer.
Solution Approach 2:
The protective insulating layer is formed in advance before the gate insulating layer deposition. This preliminary action prepares the surface in advance to resist etching damage during subsequent processing steps, preventing the harmful effects on the lower electrode before they can occur.
2Device complexity
If gate insulating layer is placed directly on lower electrode, then manufacturing process is simplified, but contact resistance increases
Solution Approach 1:
The protective insulating layer acts as an intermediary layer between the lower electrode and the gate insulating layer. This intermediate layer improves contact properties and reduces contact resistance while maintaining a relatively simple manufacturing process that only requires adding one additional layer formation step.
3Reliability
If protective insulating layer is added, then etching damage is reduced, but device structure becomes more complex
Solution Approach 1:
The protective insulating layer is applied locally at the critical interface between the lower electrode and gate insulating layer, rather than throughout the entire device structure. This localized approach provides etching damage reduction exactly where needed while minimizing the overall structural complexity and material usage.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first electrode, a second electrode, an oxide semiconductor layer provided between the first electrode and the second electrode, a gate electrode surrounding the oxide semiconductor layer, a gate insulating layer provided between the gate electrode and the oxide semiconductor layer and separated from the first electrode, a first insulating layer provided between the first electrode and the gate electrode. The gate insulating layer is between first insulating layer and the oxide semiconductor layer, and a second insulating layer is provided between the first electrode and the first insulating layer. The second insulating layer has a chemical composition or density that is different from that of the first insulating layer.