Oxide Semiconductor Transistor Stack for Low Leakage and Uniform Switching
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving small variations in transistor characteristics, high reliability, favorable electrical characteristics, high on-state current, miniaturization, and low power consumption, particularly due to issues with oxide semiconductor materials and integration density.
Innovation Solution
A semiconductor device structure is developed with specific layers and materials, including insulators, conductors, and oxides, where the second insulator is positioned between the first and second conductors, and the third and fourth oxides are strategically placed to control carrier concentrations and channel lengths, utilizing tantalum, indium, and hafnium-based materials to enhance reliability and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If oxide semiconductor materials are used to achieve low leakage current, then power consumption is reduced, but transistor characteristic variation increases
Solution Approach 1:
The patent applies parameter changes by precisely controlling the thickness of the second insulator layer (3nm-8nm) and the channel length (5nm-40nm), and by controlling carrier concentrations in different regions of the oxide semiconductor. These parameter optimizations reduce transistor characteristic variation while maintaining low leakage current properties of oxide semiconductor materials.
Solution Approach 2:
The patent implements local quality by creating distinct regions with different carrier concentrations within the oxide semiconductor layer. The second insulator is positioned to create localized electric field control, and different regions (first region contacting first conductor, second region with channel, third region overlapped by third conductor) have optimized local properties to simultaneously achieve low leakage and uniform characteristics.
2Productivity
If device size is reduced to increase integration density, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent addresses miniaturization challenges by optimizing vertical layer dimensions. The second insulator thickness is controlled at 3nm-8nm and the channel length at 5nm-40nm, utilizing the vertical stacking dimension to achieve high integration density while maintaining manufacturable precision levels for each layer.
Solution Approach 2:
The patent applies preliminary action by pre-optimizing the thickness parameters of the second insulator and the channel length before device fabrication. These parameters are predetermined within specific ranges (3nm-8nm for second insulator, 5nm-40nm for channel) to ensure that subsequent manufacturing processes can achieve the required precision more easily, reducing the burden on manufacturing control.
3Area of stationary object
If channel length is reduced to increase integration density, then device area is reduced, but transistor characteristic control becomes difficult
Solution Approach 1:
The patent controls transistor characteristics in short-channel devices by precisely setting the channel length parameter within 5nm-40nm range and optimizing the second insulator thickness at 3nm-8nm. These parameter changes enable effective electric field control despite the reduced channel length, maintaining reliable transistor operation while achieving high integration density.
Solution Approach 2:
The second insulator acts as an intermediary element between the first and second conductors, with its optimized thickness (3nm-8nm) providing appropriate electric field control and carrier concentration modulation. This intermediary layer enables reliable transistor characteristic control in miniaturized devices by mediating the interaction between electrodes and the oxide semiconductor channel.
Data Source
AI summary
A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a first conductor, a second conductor, a third oxide, a fourth oxide, and a second insulator over the second oxide; a third insulator over the first conductor, the second conductor, the third oxide, and the fourth oxide; a fourth insulator over the second insulator; and a third conductor over the fourth insulator. The second insulator is positioned between the first conductor and the second conductor. The third oxide is positioned between the first conductor and the second insulator. The fourth oxide is positioned between the second conductor and the second insulator. The thickness of the third oxide between the first conductor and the second insulator is greater than or equal to 3 nm and less than or equal to 8 nm. The thickness of the fourth oxide between the second conductor and the second insulator is greater than or equal to 3 nm and less than or equal to 8 nm.