Oxide Semiconductor Transistor Stack With MIM Capacitor Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration, large storage capacity, low manufacturing cost, and reliability while occupying a small area.
Innovation Solution
A semiconductor device is designed with a configuration that includes multiple transistors and a capacitor element, utilizing oxide semiconductors and specific insulator and conductor arrangements to optimize area usage and integration, featuring a Metal-Insulator-Metal (MIM) capacitor structure and a surrounded channel transistor structure to enhance reliability and storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional semiconductor devices are designed to achieve high integration and large storage capacity, then the device area increases, but the requirement for small footprint cannot be met
Solution Approach 1:
The patent implements a three-dimensional stacked configuration where transistor layers and capacitor elements are vertically arranged above each other. Multiple transistor layers (first transistor layer, second transistor layer) are stacked with intermediate insulating layers, and capacitor elements are positioned in different vertical levels. This vertical stacking approach increases storage capacity by utilizing the third dimension (height) rather than expanding horizontally, thereby achieving high integration while maintaining a small device footprint.
Solution Approach 2:
The patent employs a nested structure where capacitor elements are integrated within the transistor stack. The capacitor elements are positioned between and around transistor layers, with capacitor insulating layers nested within the overall device structure. This nesting approach allows multiple functional elements to occupy overlapping spatial regions, maximizing space utilization and achieving high storage capacity in a compact area.
2Area of moving object
If device area is reduced to meet small footprint requirements, then integration density increases, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor device into distinct modular layers including first transistor layer, second transistor layer, capacitor elements, and intermediate insulating layers. Each layer is formed through separate manufacturing steps with defined patterns and materials. This segmentation allows for systematic fabrication where each layer can be processed independently and then integrated, reducing overall manufacturing complexity despite the three-dimensional structure.
Solution Approach 2:
The patent uses intermediate insulating layers that serve multiple functions: they provide electrical isolation between transistor layers, serve as spacer layers for alignment, and act as structural support for subsequent layers. This multi-functionality reduces the number of separate components needed and simplifies the manufacturing process by combining multiple roles into single structural elements.
3Reliability
If oxide semiconductors are used to achieve low off-state current and high reliability, then manufacturing cost increases, but the benefit of low power consumption is achieved
Solution Approach 1:
The patent employs oxide semiconductors with specific compositional parameters (such as In-Ga-Zn-O with controlled atomic ratios) to achieve desired electrical characteristics including low off-state current and high mobility. By optimizing the chemical composition and structural parameters of the oxide semiconductor layers, the device achieves high reliability and low power consumption while using materials that can be deposited through conventional sputtering or CVD techniques, balancing performance with manufacturability.
Data Source
AI summary
A semiconductor device that occupies a small area is provided. The semiconductor device includes a first transistor including a first oxide semiconductor; a second transistor including a second oxide semiconductor; a capacitor element; a first insulator; and a first conductor in contact with a source or a drain of the second transistor. The capacitor element includes a second conductor, a third conductor, and a second insulator. The first transistor, the second transistor, and the first conductor are placed to be embedded in the first insulator. The second conductor is placed in contact with a top surface of the first conductor and a top surface of a gate of the first transistor. The second insulator is placed over the second conductor and the first insulator. The third conductor is placed to cover the second conductor with the second insulator therebetween.