Minute Oxide Semiconductor Transistor Structure for High On-State Current
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Solution Overview
Problem
Existing transistors face challenges in achieving high integration, high-speed operation, and high reliability with minute sizes, particularly in display apparatuses for XR applications, which require higher resolution and color reproducibility.
Innovation Solution
A transistor design incorporating a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, and a semiconductor layer, with specific structural configurations and fabrication methods, including the use of oxide semiconductors and controlled layer widths and densities, to enhance electrical characteristics and productivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to achieve high integration, then the degree of integration is improved, but manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The transistor is divided into multiple functional layers including a semiconductor layer, first gate electrode, second gate electrode, source electrode, and drain electrode. Each layer is formed through separate fabrication steps with specific structures (e.g., the gate electrodes are positioned at different heights and have different widths), allowing precise control of each component independently while maintaining overall miniaturization for high integration
Solution Approach 2:
Different regions of the transistor structure have different properties: the first gate electrode has a first width and is positioned at a first height, while the second gate electrode has a second width and is positioned at a second height. The source and drain electrodes have different widths and are positioned at different heights. This local differentiation allows optimization of electrical characteristics in each region while maintaining compact overall dimensions for high integration
2Productivity
If transistor size is reduced to achieve high integration, then the degree of integration is improved, but on-state current decreases
Solution Approach 1:
The transistor utilizes a three-dimensional structure with gate electrodes positioned at different heights above the semiconductor layer. The first gate electrode is at a first height and the second gate electrode is at a second height, creating vertical stacking that increases the effective gate control area without increasing the planar footprint. This dimensional approach allows maintaining high on-state current while achieving miniaturization for high integration
Solution Approach 2:
The transistor employs a composite structure with multiple materials: a semiconductor layer (which may be oxide semiconductor), conductive materials for gate electrodes and source/drain electrodes, and insulating materials for isolation. This composite approach optimizes electrical characteristics including on-state current while enabling compact device dimensions for high integration
3Productivity
If transistor size is reduced to achieve high integration, then the degree of integration is improved, but electrical characteristics deteriorate
Solution Approach 1:
The transistor is segmented into distinct functional regions with the first gate electrode controlling one interface and the second gate electrode controlling another interface of the semiconductor layer. Each electrode has specific dimensional characteristics (different widths and heights) that optimize their respective functions. This segmentation allows independent optimization of electrical characteristics while maintaining miniaturized dimensions for high integration
Solution Approach 2:
Different portions of the transistor structure have tailored properties: the first gate electrode has a first width optimized for its control region, the second gate electrode has a second width optimized for its control region, and the source/drain electrodes have different widths and heights. This local quality optimization ensures excellent electrical characteristics in each region while maintaining overall compact size for high integration
Data Source
AI summary
A transistor having a minute size is provided. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, and a semiconductor layer. The first insulating layer is provided over the first conductive layer and includes an opening reaching the first conductive layer and a depressed portion surrounding the opening in a plan view. The second conductive layer is provided to cover the inner wall of the depressed portion and includes a region facing the semiconductor layer with the first insulating layer therebetween. The semiconductor layer is provided to include a region overlapping with the opening and is in contact with the top surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second conductive layer, and the top surface of the second conductive layer. The second insulating layer is provided in contact with the top surface of the semiconductor layer. The third conductive layer is provided over the second insulating layer to cover the inner wall of the opening and includes a region facing the semiconductor layer with the second insulating layer therebetween.