Oxide Semiconductor Transistor Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Miniaturized transistors face challenges with increased electric field concentration at end portions of source and drain electrode layers and parasitic capacitance between gate and source/drain electrode layers, which affect their performance and reliability.
Innovation Solution
A transistor structure is developed with oxide semiconductor layers, where the source and drain electrode layers have regions projecting in the channel length direction, and an additional insulating layer is provided between these layers and the gate electrode layer, reducing electric field concentration and parasitic capacitance through a specific geometry and material configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistor miniaturization is pursued to achieve high speed operation, then device speed and integration density are improved, but electric field concentration at end portions of source and drain electrode layers increases causing reliability degradation
Solution Approach 1:
The patent applies local quality by creating a multi-layer source/drain electrode structure where different layers have different widths. Specifically, the first conductive layer has a first width and the second conductive layer has a second width that is different from the first width. This local variation in geometric properties allows the structure to simultaneously achieve miniaturization while controlling electric field distribution at critical regions, thereby maintaining reliability during scaling.
Solution Approach 2:
The patent employs composite materials by constructing the source/drain electrode as a stack of multiple conductive layers with different materials and geometric configurations. The first conductive layer and second conductive layer are combined to form a composite electrode structure that optimizes both electrical performance and electric field management, enabling high-speed operation without compromising reliability in miniaturized transistors.
2Speed
If transistor miniaturization is pursued to achieve high speed operation, then device speed and integration density are improved, but parasitic capacitance between gate electrode layer and source/drain electrode layers increases
Solution Approach 1:
The patent reduces parasitic capacitance by applying local quality principles to the electrode geometry. The first conductive layer and second conductive layer are designed with different widths, creating localized geometric variations that minimize the overlapping area between the gate electrode layer and source/drain electrode layers. This localized optimization of geometric properties directly reduces parasitic capacitance while maintaining the transistor's high-speed performance capability.
Solution Approach 2:
The patent addresses parasitic capacitance by introducing dimensional variation in the vertical stacking of conductive layers. The first conductive layer and second conductive layer are arranged in different vertical positions with different horizontal extents, utilizing the third dimension (vertical stacking) to control the capacitive coupling area. This dimensional approach allows reduction of parasitic capacitance without sacrificing the horizontal integration density needed for high-speed operation.
Data Source
AI summary
A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.