Top-Gate Bottom-Contact Oxide Transistor for Short-Channel Stability
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Solution Overview
Problem
Miniaturization of transistors leads to fluctuations in electric characteristics, such as decreased threshold voltage, due to the short-channel effect, which is challenging to suppress, especially in oxide semiconductor devices with thin channel lengths.
Innovation Solution
The introduction of regions with varying dopant concentrations in the oxide semiconductor film, specifically two pairs of amorphous regions with different dopant concentrations, helps to relieve the electric field in the channel formation region, thereby suppressing the short-channel effect. Additionally, using a c-axis aligned crystal (CAAC) oxide semiconductor in the channel formation region improves the reliability and reduces fluctuations in electric characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the channel length is shortened to achieve miniaturization, then the transistor size is reduced and integration is improved, but the threshold voltage fluctuates and the short-channel effect increases
Solution Approach 1:
The patent applies local quality by creating dopant concentration gradients within the oxide semiconductor film. Specifically, the source and drain regions are doped at higher concentrations than the channel formation region, and the dopant concentration is further increased in the regions adjacent to the source and drain electrodes. This localized variation in dopant concentration allows the channel length to be shortened while maintaining threshold voltage stability through the electric field relief effect of the high-concentration dopant regions.
2Length of stationary object
If the oxide semiconductor layer thickness is reduced to less than or equal to 20 nm to prevent short-channel effect, then the channel control is improved, but plasma treatment causes overetching and increases resistance
Solution Approach 1:
The patent applies preliminary action by forming the gate insulating film and gate electrode before performing plasma treatment. The gate insulating film serves as a protective layer during subsequent plasma processing steps, preventing overetching of the thin oxide semiconductor layer (thickness ≤ 20 nm). This allows the source and drain regions to be properly formed without excessive etching, thereby maintaining manufacturing precision while enabling the use of thin oxide semiconductor layers for short-channel transistor design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces fluctuations in electric characteristics, enhances the reliability of the semiconductor device, and allows for further miniaturization of transistors without significant increases in resistance or defective products.
Implementation Method 1
using a c-axis aligned crystal (CAAC) oxide semiconductor in the channel formation region improves the reliability and reduces fluctuations in electric characteristics
Implementation Method 2
The introduction of regions with varying dopant concentrations in the oxide semiconductor film, specifically two pairs of amorphous regions with different dopant concentrations, helps to relieve the electric field in the channel formation region
Data Source
AI summary
A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.