Oxide Semiconductor Transistor Sidewall Structure for Short-Channel Effect
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Solution Overview
Problem
Miniaturization of transistors leads to a short-channel effect, which degrades electric characteristics, and requires precise alignment for Lov region formation, making it challenging to maintain favorable characteristics and suppress on-state current decrease.
Innovation Solution
A semiconductor device structure is developed with a source and drain electrode layer in contact with an oxide semiconductor layer on side surfaces, and conductive sidewall layers are formed over these electrodes with a gate insulating layer in between, allowing for a Lov region to be created, thus reducing the short-channel effect and maintaining on-state current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the transistor is miniaturized to achieve high-speed operation and low power consumption, then the transistor size is reduced, but the short-channel effect occurs which degrades electric characteristics
Solution Approach 1:
The invention introduces a new spatial dimension by forming sidewall layers on the side surfaces of the gate electrode. This three-dimensional structure creates an overlap region between the gate electrode and source/drain electrodes without increasing the planar footprint, thereby achieving electric field control in the vertical dimension while maintaining miniaturization in the horizontal dimension.
Solution Approach 2:
The sidewall layers act as intermediary structures that mediate between the gate electrode and source/drain electrodes. These conductive or highly-doped semiconductor sidewall layers create the necessary electric field control and overlap effects without requiring direct contact or precise alignment between the gate and source/drain electrodes, thus resolving the short-channel effect while maintaining manufacturing feasibility.
2Reliability
If the Lov region is formed by precise alignment between oxide semiconductor layer and gate electrode layer to suppress decrease in on-state current, then the on-state current is maintained, but the manufacturing precision requirement increases significantly
Solution Approach 1:
The sidewall layers are formed on the side surfaces of the gate electrode before final electrode patterning, establishing the overlap region geometry in advance. This preliminary structuring ensures that the Lov region is created through the sidewall layer positioning rather than requiring precise alignment between separately formed oxide semiconductor and gate electrode layers, thereby reducing manufacturing precision requirements.
Solution Approach 2:
The sidewall layers automatically define the overlap region boundaries through their positioning on the gate electrode side surfaces. This self-aligning mechanism eliminates the need for external alignment control between different lithography steps, as the Lov region is inherently determined by the sidewall layer formation process rather than requiring precise registration between multiple layers.
Data Source
AI summary
A miniaturized transistor having favorable electric characteristics is provided. The transistor includes an oxide semiconductor layer which is in contact with a source electrode layer on one of side surfaces in a channel length direction and in contact with a drain electrode layer on the other of the side surfaces in the channel length direction. With this structure, an electric field between the source electrode layer and the drain electrode layer is relaxed and a short-channel effect is suppressed. Further, a sidewall layer having conductivity is provided on a side surface of a gate electrode layer in the channel length direction, so that the sidewall layer having conductivity overlaps with the source electrode layer or the drain electrode layer with a gate insulating layer provided therebetween, which enables the transistor to substantially have an Lov region.