Oxide Semiconductor Transistor Doping for Low-Resistance Source/Drain
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high-speed operation, minimizing variation in electric characteristics due to short channel effects, reducing contact resistance, and ensuring reliable formation of source and drain regions with low resistance, especially when using thin oxide semiconductor layers.
Innovation Solution
A semiconductor device is designed with a gate electrode, gate insulating layer, and an oxide semiconductor layer having crystallinity, where the oxide semiconductor layer includes a channel formation region and pair of source and drain regions with specific dopant addition methods to reduce resistance and prevent thinning, using c-axis aligned crystalline oxide semiconductor (CAAC-OS) and rare gas or hydrogen dopants to improve conductivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If argon plasma treatment is performed on the exposed surface of the oxide semiconductor to form source and drain regions, then the source and drain regions are formed by self-aligned process, but the oxide semiconductor regions are etched and thinned, increasing resistance and producing defective units
Solution Approach 1:
A channel protective layer is introduced as an intermediary between the oxide semiconductor layer and the plasma treatment environment. This protective layer prevents direct plasma damage to the oxide semiconductor during source and drain region formation, eliminating etching and thinning while maintaining the self-aligned process advantage.
Solution Approach 2:
The channel protective layer is formed preliminarily before plasma treatment to protect the oxide semiconductor layer. This preliminary protective action prevents damage before it occurs, allowing subsequent plasma processing to form source and drain regions without etching the channel region.
2Length of moving object
If the oxide semiconductor layer is made thin to prevent short channel effect in miniaturized transistors, then the channel length can be reduced, but plasma treatment causes excessive thinning and increases resistance
Solution Approach 1:
The channel protective layer serves as a mediator that enables precise thickness control of the oxide semiconductor layer. By protecting the layer during plasma processing, the actual thickness is maintained as designed, allowing miniaturization without excessive thinning or resistance increase.
3Speed
If the oxide semiconductor layer is made thin to achieve high-speed operation, then the channel length can be reduced, but contact resistance increases due to plasma etching
Solution Approach 1:
The channel protective layer acts as a protective intermediary during source and drain formation, preventing plasma-induced etching and thinning of the oxide semiconductor. This maintains adequate thickness for low contact resistance while still enabling high-speed operation through controlled miniaturization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-speed operation, minimizes short channel effects, reduces contact resistance, and enhances the reliability and miniaturization of semiconductor devices by forming source and drain regions with lower resistance than the channel region, resulting in improved on-state current and reduced off-state current.
Implementation Method 1
The use of a c-axis aligned crystalline oxide semiconductor (CAAC-OS) with a channel formation region and paired source/drain regions
Implementation Method 2
controlled dopant addition through ion doping
Data Source
AI summary
A semiconductor device capable of high speed operation is provided. Further, a highly reliable semiconductor device is provided. An oxide semiconductor having crystallinity is used for a semiconductor layer of a transistor. A channel formation region, a source region, and a drain region are formed in the semiconductor layer. The source region and the drain region are formed in such a manner that one or more of elements selected from rare gases and hydrogen are added to the semiconductor layer by an ion doping method or an ion implantation method with the use of a channel protective layer as a mask.