Oxide Transistor Structure for High Integration and On-State Current
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration, miniaturization, and high on-state current while maintaining favorable electrical characteristics and reliability, particularly for applications in high-resolution display apparatuses such as those used in extended reality (XR) technologies.
Innovation Solution
A semiconductor device design incorporating a first and second transistor configuration, where the transistors are arranged with high density and connected through specific conductive and insulating layers, utilizing oxide semiconductors and controlled oxygen supply to enhance transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If transistors are miniaturized to increase integration density, then the degree of integration is improved, but the on-state current decreases
Solution Approach 1:
The patent applies local quality by creating a dual-gate transistor structure where the second gate electrode is positioned adjacent to the channel formation region to provide localized electric field control. This localized gating mechanism enhances carrier concentration and mobility in the channel region, thereby improving on-state current without increasing the overall transistor footprint, thus resolving the contradiction between miniaturization and current maintenance.
Solution Approach 2:
The patent transitions from a conventional single-gate planar structure to a three-dimensional dual-gate configuration where the second gate electrode extends along the channel formation region. This dimensional addition creates multiple control points for the channel, enabling enhanced electrical characteristics within a compact area, thus achieving high integration density while maintaining strong on-state current.
2Device complexity
If transistors are arranged with high density, then the degree of integration is improved, but the electrical characteristics deteriorate
Solution Approach 1:
The patent implements local quality through the dual-gate structure where the second gate electrode provides localized electric field enhancement specifically in the channel formation region. This localized control improves carrier transport properties and reduces variability in electrical characteristics even when transistors are densely packed, thereby maintaining reliability while achieving high integration.
Solution Approach 2:
The patent applies preliminary action by forming the insulating layer with specific oxygen concentration before transistor fabrication, and by positioning the second gate electrode to pre-establish optimal electric field distribution. These preliminary structural preparations ensure favorable electrical characteristics are built into the device architecture before operation, enabling high-density arrangement without characteristic deterioration.
3Power
If oxide semiconductors are used to enhance transistor performance, then the on-state current is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent applies parameter changes by controlling the oxygen concentration in the insulating layer to be 1×10^19 to 1×10^21 atoms/cm³, which optimizes the electrical characteristics of the oxide semiconductor channel. By precisely controlling this material parameter during fabrication, the process achieves enhanced on-state current through standardized manufacturing steps rather than complex post-processing, thus improving performance while managing manufacturing complexity.
Data Source
AI summary
A semiconductor device (10) having a high degree of integration is provided. A first and a second transistors which are electrically connected to each other and a first insulating layer (110) are included. The first transistor (M2) includes a first semiconductor layer (108), a second insulating layer (106), and a first to a third conductive layers. The second transistor (M1) includes a second semiconductor layer (109), a third insulating layer (106), and a fourth to a sixth conductive layers. The first insulating layer is positioned over the first conductive layer (112a) and includes an opening reaching the first conductive layer. The second conductive layer (112b) is positioned over the first insulating layer. The first semiconductor layer is in contact with a top surface of the first conductive layer, an inner wall of the opening, and the second conductive layer. The third conductive layer (104) is positioned over the second insulating layer to overlap with the inner wall of the opening. The third insulating layer is positioned over the fourth conductive layer (112b). The second semiconductor layer is positioned over the third insulating layer to overlap with the fourth conductive layer. In a cross-sectional view, a top surface of one side end portion of the second semiconductor layer is in contact with the fifth conductive layer (116a). A top surface of the other side end portion facing the one side end portion is in contact with the sixth conductive layer (116b).