Oxidized Gate Sidewalls for Lower Parasitic Capacitance
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Solution Overview
Problem
The challenge in the semiconductor industry is to reduce parasitic capacitance and improve gate isolation structures in multi-gate devices like FinFETs and GAA FETs, particularly due to the presence of gate footings which complicate the formation of satisfactory gate isolation and increase parasitic capacitance as feature sizes decrease.
Innovation Solution
The method involves oxidizing the side portions and gate footings of dummy gate electrodes to form dielectric gate spacers, which increases the distance between the gate structure and source/drain contacts, thereby reducing parasitic capacitance and enabling effective gate isolation without additional lithography or etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate footings are present in conventional FinFET structures, then the gate structure can be formed using standard lithography processes, but parasitic capacitance between the gate and source/drain contacts increases
Solution Approach 1:
The patent removes the gate footing structure from the conventional FinFET design. By eliminating the gate footing that extends beyond the channel region, the harmful parasitic capacitance between the gate and source/drain contacts is reduced. The gate structure is precisely aligned to end at the channel boundary without extending into the source/drain contact regions.
Solution Approach 2:
The patent introduces a multi-layer gate structure with different functional regions at different vertical levels. The gate structure includes a gate electrode layer and a gate dielectric layer, where the gate electrode can be selectively removed in certain regions while the gate dielectric remains, creating a differentiated structure that reduces parasitic capacitance while maintaining manufacturing feasibility.
2Area of moving object
If feature sizes are reduced to increase functional density, then IC chip footprint is reduced, but parasitic capacitance between gate and source/drain contact increases
Solution Approach 1:
The patent applies different structural characteristics to different regions of the gate structure. In the channel region, the complete gate structure (electrode and dielectric) is maintained for proper device operation. In the regions adjacent to source/drain contacts, the gate electrode is selectively removed while the gate dielectric remains, creating a localized modification that reduces parasitic capacitance without affecting the overall device functionality.
Solution Approach 2:
The gate structure is segmented into functionally distinct regions: a full gate region over the channel and a modified gate region adjacent to source/drain contacts. This segmentation allows the gate electrode to be present where needed for device operation and absent where it would create harmful parasitic capacitance, enabling continued scaling while managing parasitic effects.
3Ease of manufacture
If gate footings are used to simplify gate structure formation, then manufacturing process is easier, but gate isolation structure formation becomes more complex
Solution Approach 1:
The patent removes the gate footing structure that complicates gate isolation formation. Without gate footings extending beyond the channel region, the gate isolation structures can be formed more simply and positioned more precisely, reducing the complexity of the overall fabrication process while maintaining ease of gate structure formation through the multi-layer approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and facilitates the formation of satisfactory gate isolation structures, enhancing the reliability and performance of semiconductor devices by increasing the distance between the gate and source/drain contacts.
Implementation Method 1
oxidizing the side portions and gate footings of dummy gate electrodes to form dielectric gate spacers
Data Source
AI summary
Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary method includes depositing a dummy gate material layer over a first fin-shaped active region, patterning the dummy gate material layer to form a dummy gate electrode, wherein the dummy gate electrode has a footing feature at an interface between the first fin-shaped active region and the dummy gate electrode, oxidizing the footing feature and a sidewall portion of the dummy gate electrode to form a dielectric gate spacer, and replacing a remaining portion of the dummy gate electrode with a gate structure.