Oxidized Interface Memory Layer for Uniform Thin Film Deposition
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Solution Overview
Problem
In resistance change type semiconductor memory devices, it is challenging to thin the memory layer while maintaining uniformity and suppressing dispersion in electrical characteristics among elements, which affects both chip size and operational voltage requirements.
Innovation Solution
The memory layer is formed by oxidizing the surface of either the first electrode or the ion source layer, creating a resistance change type memory layer at the interface between the two, which allows for thinner layers with improved step coverage and reduced electrical dispersion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the memory layer is thinned to reduce chip size and operational voltage, then the chip size and power consumption are reduced, but the step coverage deteriorates and electrical characteristics become dispersed
Solution Approach 1:
A flatting layer is formed on the first electrode before forming the memory layer. This preliminary action creates a flat surface that enables subsequent memory layer deposition with excellent step coverage and uniform thickness, even when the memory layer is thin. The flatting layer pre-compensates for surface irregularities, allowing the memory layer to be formed with controlled thickness and good coverage.
2Use of energy by moving object
If the memory layer is thinned to reduce operational voltage, then the operational voltage and power consumption are reduced, but the electrical characteristics become dispersed
Solution Approach 1:
The flatting layer is formed in advance to provide a flat surface for memory layer deposition. This preliminary surface preparation ensures that even thin memory layers can be formed with uniform thickness and good step coverage, resulting in consistent electrical characteristics across the device while enabling lower operational voltages.
Solution Approach 2:
By changing the surface morphology parameter (creating a flat surface with the flatting layer), the deposition process parameters can be optimized to achieve uniform thin memory layers with controlled thickness. This parameter change enables the memory layer to be thin enough for low voltage operation while maintaining uniform electrical characteristics through improved deposition control.
3Area of stationary object
If the memory layer is thinned to reduce chip size, then the chip size is reduced, but the step coverage deteriorates
Solution Approach 1:
The flatting layer is formed as a preliminary structure before the memory layer deposition. This preliminary action creates a flat surface that dramatically improves step coverage, allowing the memory layer to conform uniformly to the underlying structure even at reduced thicknesses, thereby enabling smaller chip size without sacrificing step coverage quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the thinning of the memory layer while ensuring high step coverage and uniform thickness, reducing operational voltage and power consumption, and improving the stability and reliability of the memory device.
Implementation Method 1
either a surface of the first electrode or a surface of the ion source layer is oxidized to form a resistance change type memory layer
Data Source
AI summary
Disclosed herein is a semiconductor memory device, including: a first electrode formed on a substrate; an ion source layer formed on an upper layer of the first electrode; and a second electrode formed on an upper layer of the ion source layer. Resistance change type memory cells in each of which either a surface of the first electrode or a surface of the ion source layer is oxidized to form a resistance change type memory layer in an interface between the first electrode and the ion source interface are arranged in a array.