Oxidized Semiconductor Sacrificial Layer for NAND Memory Fabrication
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Solution Overview
Problem
The existing methods for forming arrays of elevationally-extending memory cells, particularly in NAND architecture, face challenges such as material etching issues that can lead to failed circuitry, especially when etching materials like silicide under polysilicon, which can result in damaged control or other circuitry.
Innovation Solution
The method involves forming conductively-doped semiconductor material directly above and electrically coupled to metal material, with a stack of vertically-alternating insulative and wordline tiers, and oxidizing the semiconductor material through trenches to form an oxide layer, while ensuring the wordline tiers comprise control-gate material with terminal ends corresponding to control-gate regions of individual memory cells, and including a charge-blocking region between the charge-storage and control-gate regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form NAND memory cells, then memory cell structure can be formed, but underlying control circuitry may be damaged due to material etching issues
Solution Approach 1:
A sacrificial layer is introduced as an intermediary component between the memory cell structure and the control circuitry. This sacrificial layer acts as a protective mediator during the etching process, preventing direct contact between etching chemicals and the control circuitry while still allowing the memory cell structure to be formed above it. After the memory cell formation is complete, the sacrificial layer is removed, having served its protective purpose.
Solution Approach 2:
The sacrificial layer is formed in advance before the memory cell structure is built. This preliminary action establishes a protective barrier prior to the etching process, ensuring that the control circuitry is protected from potential damage during subsequent manufacturing steps. The protective structure is prepared beforehand rather than attempting to protect the circuitry during the etching process itself.
2Productivity
If vertically-stacked memory cells are formed with control circuitry below, then three-dimensional memory architecture is achieved, but etching materials above can damage the control circuitry below
Solution Approach 1:
The sacrificial layer serves as a protective intermediary positioned between the vertically-stacked memory cells and the control circuitry. During the etching process used to form the memory cell structures, this sacrificial layer absorbs or blocks the harmful effects of etching chemicals, preventing them from reaching and damaging the control circuitry below while allowing the three-dimensional memory architecture to be constructed.
Solution Approach 2:
The sacrificial layer provides beforehand cushioning or protection to the control circuitry. By placing this protective layer in advance, the system is cushioned against the harmful effects of etching processes. The sacrificial layer acts as a buffer that absorbs the impact of aggressive etching chemicals, protecting the underlying control circuitry from damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively forms elevationally-extending strings of memory cells without damaging underlying circuitry, enhancing the reliability and integrity of the memory cell array by controlling the etching process and ensuring proper formation of oxide layers and charge-blocking regions.
Implementation Method 1
The conductively-doped semiconductor material is oxidized through the trenches to form an oxide therefrom that is directly above the metal material
Data Source
AI summary
A method of forming an array of elevationally-extending strings of memory cells comprises forming conductively-doped semiconductor material directly above and electrically coupled to metal material. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed directly above the conductively-doped semiconductor material. Horizontally-elongated trenches are formed through the stack to the conductively-doped semiconductor material. The conductively-doped semiconductor material is oxidized through the trenches to form an oxide therefrom that is directly above the metal material. Transistor channel material is provided to extend elevationally along the alternating tiers. The wordline tiers are provided to comprise control-gate material having terminal ends corresponding to control-gate regions of individual memory cells. Charge-storage material is between the transistor channel material and the control-gate regions. Insulative charge-passage material is between the transistor channel material and the charge-storage material. A charge-blocking region is between the charge-storage material and individual of the control-gate regions.