Oxidized Silicon Liner for Fin Isolation With Lower Charge Trapping
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Solution Overview
Problem
In the formation of FinFETs, existing technologies face challenges in generating beneficial strain and reducing charge trapping in the channel, particularly due to the use of silicon nitride liners which are prone to high leakage currents and charge trapping.
Innovation Solution
The formation of a silicon liner followed by oxidation into a silicon oxide liner, which increases volume and generates beneficial strain in the channel, reducing charge trapping and improving tensile strain, is achieved through a conformal deposition process and subsequent annealing in an oxygen-containing environment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon nitride liners are used in isolation region formation, then isolation regions can be formed, but high leakage currents and charge trapping occur in the channel
Solution Approach 1:
The patent removes the silicon nitride liner material from the isolation region formation process. Instead of using silicon nitride, the invention employs a silicon oxide liner formed by depositing a silicon-containing layer and oxidizing it. This extraction of the problematic material eliminates the source of charge trapping and leakage current issues while maintaining the isolation region formation capability.
Solution Approach 2:
The patent changes the material composition parameter of the liner from silicon nitride to silicon oxide. This parameter change fundamentally alters the electrical characteristics of the liner, reducing leakage current and charge trapping. The oxidation process transforms the silicon-containing layer into silicon oxide, which has superior electrical properties for preventing charge trapping in the channel.
2Strength
If silicon liner is oxidized into silicon oxide liner, then beneficial strain and tensile strain are generated in the channel, but the process complexity increases
Solution Approach 1:
The patent combines the liner formation and oxidation steps into an integrated process sequence. The silicon-containing layer is deposited conformally and then oxidized in situ to form the silicon oxide liner. This merging of steps generates beneficial tensile strain in the channel through the oxidation-induced volume expansion, while consolidating the process to minimize overall complexity.
Solution Approach 2:
The patent utilizes the phase transition of silicon to silicon oxide through oxidation. When the silicon-containing layer is oxidized, it undergoes a chemical phase change that results in volume expansion. This phase transition generates beneficial compressive and tensile strain in the channel region, improving carrier mobility and device performance without requiring additional strain engineering steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of FinFETs by improving tensile stress by 0.3% and reducing charge trapping, while avoiding the high leakage currents associated with silicon nitride liners.
Implementation Method 1
oxidizing the silicon-containing layer to form a first liner. The first liner comprises oxidized silicon.
Data Source
AI summary
A method includes etching a semiconductor substrate to form a trench and a semiconductor strip. A sidewall of the semiconductor strip is exposed to the trench. The method further includes depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip, filling the trench with a dielectric material, wherein the dielectric material is on a sidewall of the silicon-containing layer, and oxidizing the silicon-containing layer to form a liner. The liner comprises oxidized silicon. The liner and the dielectric material form parts of an isolation region. The isolation region is recessed, so that a portion of the semiconductor strip protrudes higher than a top surface of the isolation region and forms a semiconductor fin.