Co-integrating OxRAM Memory and FET Transistors in Single Layer
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Solution Overview
Problem
Current OxRAM memory technologies face challenges in miniaturization, power consumption, and manufacturing complexity, particularly in integrating memory cells and selection transistors, which affect integration density and access time.
Innovation Solution
The method involves co-integrating OxRAM memory cells and their selection transistors in the same layer before metallization, using common materials and deposition steps, allowing for a simplified manufacturing process and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a field effect transistor is added to select a memory point, then access time is optimized and current is limited, but integration density is greatly reduced due to the transistor occupying non-negligible substrate area
Solution Approach 1:
The patent merges the selection transistor and memory cell into a single integrated structure where the transistor is formed within the same deposition layer as the memory cell. The transistor gate, source, and drain are co-formed with the memory cell electrodes and insulating layers, eliminating the need for separate transistor structures and reducing overall substrate area while maintaining selection functionality.
Solution Approach 2:
The insulating layer serves multiple functions: it acts as the gate insulator for the selection transistor, the dielectric material for the memory cell, and the medium in which the conductive filament forms. This multi-functionality reduces the number of separate layers and components needed, thereby reducing substrate area while maintaining reliable access control.
2Area of stationary object
If selection transistors are integrated in a layer before metallization with memory points in a layer after metallization, then integration density is improved, but manufacturing process complexity is markedly increased
Solution Approach 1:
The patent combines the transistor and memory cell formation into a single deposition layer and set of processing steps. Both structures are formed simultaneously using the same insulating layer, electrode materials, and deposition processes, eliminating the need for separate pre-metallization and post-metallization layers and their associated complex manufacturing steps.
Solution Approach 2:
The selection transistor components (gate, source, drain) are formed in advance within the same layer as the memory cell, with proper spatial arrangement and electrical isolation established during the initial deposition process. This preliminary integration simplifies subsequent processing steps while achieving high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the surface area occupied by memory cells on the substrate, enhances integration density, and simplifies the manufacturing process, while maintaining efficient access times and reducing power consumption.
Implementation Method 1
the conductive filament is made from oxygen vacancies in an insulating material based on metal oxide
Implementation Method 2
a dielectric material, which is normally insulating, can be forced to be conductive through a filament or a conduction path after the application of sufficiently high voltage
Data Source
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AI summary
The invention relates to a method for manufacturing an integrated circuit (1), comprising the steps of: - providing a substrate (100), the substrate being provided with first and second dummy gates and an encapsulation layer (106); - removing the first and second dummy gates to provide first and second grooves (23,33) in said encapsulation layer (106); - simultaneously depositing a layer of gate insulator (107) at least in the bottom of the first groove and on a lateral wall of the second groove; - forming a gate electrode of said transistor (2) in the first groove, forming source and drain electrodes of said transistor on either side of said gate electrode, forming first and second electrodes of said memory cell on either side of said layer of gate insulator deposited on a lateral wall of the second groove.