Oxygen-Doped Polysilicon Stack for RF SOI PSC Suppression

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Solution Overview

Problem

Silicon-on-insulator (SOI) substrates for radio frequency (RF) applications face parasitic surface conduction (PSC) issues due to fixed charge in the insulator layer attracting free charge carriers, leading to RF losses and crosstalk, which conventional trap-rich polysilicon layers struggle to fully mitigate despite reduced grain sizes.

Innovation Solution

Embedding layers of oxygen-doped polysilicon between polysilicon layers to increase grain boundaries and form dangling bonds, effectively trapping free charge carriers and reducing PSC, thereby minimizing RF losses and crosstalk.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If conventional trap-rich polysilicon layers are used to reduce parasitic surface conduction, then some PSC mitigation is achieved, but RF losses and crosstalk cannot be fully eliminated

Engineering Contradiction:
Improveparasitic surface conductionVSAvoidRF performance
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent uses a composite structure consisting of multiple polysilicon layers with different oxygen concentrations (ranging from 10^19 to 10^21 atoms/cm³). This multi-layer composite approach creates varying trap densities throughout the structure, providing enhanced charge carrier trapping capability that single-layer designs cannot achieve, thereby fully eliminating PSC while maintaining RF performance

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The polysilicon structure is divided into multiple discrete layers with progressively increasing oxygen concentrations. Each layer segment provides a specific trap density profile, and the cumulative effect of these segmented layers creates a more effective barrier against parasitic surface conduction than any single uniform layer could provide

Inventive Principle:
Principle #1Segmentation

2Object-affected harmful factors

If polysilicon grain size is reduced to increase grain boundaries for trapping, then trapping capacity improves, but manufacturing complexity and process control difficulty increase

Engineering Contradiction:
Improvecharge carrier trappingVSAvoidpolysilicon layer structure
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

Instead of controlling grain size through complex processing parameters, the patent changes the oxygen concentration parameter in each polysilicon layer. This parameter change directly controls trap density without requiring precise grain size control, simplifying the manufacturing process while achieving enhanced charge carrier trapping through the multi-layer structure

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The use of oxygen-doped polysilicon layers significantly reduces parasitic surface conduction, mitigating RF losses and crosstalk, and improving the linearity of RF devices by increasing the number of trapping mechanisms for free charge carriers.

Implementation Method 1

Embedding layers of oxygen-doped polysilicon between polysilicon layers to increase grain boundaries and form dangling bonds, effectively trapping free charge carriers

Methodology Applied
Scientific EffectGrain boundary trapping:

Implementation Method 2

Embedding layers of oxygen-doped polysilicon between polysilicon layers to increase grain boundaries and form dangling bonds, effectively trapping free charge carriers

Methodology Applied
Scientific EffectDangling bonds trapping:

Data Source

PatentUS12074036B2Multi-layered polysilicon and oxygen-doped polysilicon design for RF SOI trap-rich poly layer
Publication Date: 2024.08.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12074036B2 patent drawing
  • US12074036B2 patent drawing
  • US12074036B2 patent drawing

AI summary

In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.