Oxygen-Free Offset Spacers for High-K Gate Dielectric Protection
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Solution Overview
Problem
As semiconductor device feature sizes shrink below 0.25 microns, existing methods fail to effectively form spacers that improve MOSFET device performance by controlling strain on the channel region and preventing sub-oxide formation in high-K gate dielectrics, which degrades device performance.
Innovation Solution
The use of oxygen-free offset spacers, specifically I-shaped and L-shaped strained spacers, are formed over NMOS and PMOS gate structures respectively, using stressed dielectric layers to induce desired strain and protect high-K gate dielectrics from sub-oxide formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional offset spacers are used in high-K MOSFET devices, then device performance may be maintained, but sub-oxide formation occurs in the high-K gate dielectric under gate edge regions, degrading device performance
Solution Approach 1:
An oxygen-free dielectric material is introduced as an intermediary layer between the offset spacer and the high-K gate dielectric. This intermediary material prevents oxygen diffusion into the high-K dielectric, thereby eliminating sub-oxide formation while maintaining the electrical performance benefits of the offset spacer structure.
Solution Approach 2:
The offset spacer structure is formed as a composite of multiple materials: a conductive or doped material for electrical functionality, and an oxygen-free dielectric material for protection. This composite structure simultaneously provides electrical performance and prevents harmful oxygen diffusion into the high-K gate dielectric.
2Reliability
If offset spacers are formed to control strain on the channel region, then device characteristics such as threshold voltage roll-off and DIBL are improved, but the formation process becomes more complex
Solution Approach 1:
The offset spacer formation process is segmented into distinct functional layers: a strain-inducing layer that controls channel strain, and an oxygen-free dielectric layer that protects the high-K gate dielectric. This segmentation allows each layer to be optimized for its specific function while simplifying the overall process control.
Solution Approach 2:
Different regions of the offset spacer structure are assigned different materials and properties: the region adjacent to the channel region is designed to induce strain, while the region adjacent to the high-K gate dielectric is designed to be oxygen-free for protection. This local differentiation achieves multiple objectives simultaneously without increasing overall process complexity.
3Productivity
If feature sizes are scaled below 0.25 microns, then device density and integration are improved, but conventional spacer formation methods fail to provide adequate strain control and protection
Solution Approach 1:
The offset spacer structure is extended into the vertical dimension with multiple layers having different functions. The strain-inducing layer and oxygen-free dielectric layer are stacked vertically, allowing independent optimization of strain control and protection functions while maintaining compact lateral dimensions for high device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by selectively straining the channel region and preventing sub-oxide formation, thereby improving threshold voltage roll-off, drain-induced barrier lowering, and subthreshold swing variation, while maintaining equivalent oxide thickness (EOT) and device polarity performance.
Implementation Method 1
each comprising a stressed dielectric layer, to induce a desired strain on a respective channel region
Implementation Method 2
the oxygen-free offset spacer portions adjacent either side of the first gate structure and the oxygen-free offset spacer portions adjacent either side of the second gate structure are formed with different shapes... sealing respective high-K gate dielectric sidewall portions
Data Source
AI summary
A semiconductor device pair is provided. The semiconductor device pair comprises a semiconductor substrate comprising a first gate structure with a first type polarity and a second gate structure with a second type polarity, the first and the second gate structures comprise a high-K gate dielectric. A plurality of oxygen-free offset spacer portions are adjacent either side of the respective first and second gate structures, each comprising a stressed dielectric layer, to induce a desired strain on a respective channel region while sealing respective high-K gate dielectric sidewall portions, wherein the oxygen-free offset spacer portions adjacent either side of the first gate structure and the oxygen-free offset spacer portions adjacent either side of the second gate structure are formed with different shapes.