Oxygen Neutralization for Wafer Charge Release

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Solution Overview

Problem

High joint test action group (JTAG) failure rates in integrated circuit manufacturing, particularly in input/output chips, due to damage from charge accumulation during via-etching processes, where chips over lift pins in electrostatic chucks experience high discharging currents, leading to polysilicon and gate dielectric damage.

Innovation Solution

Incorporating an oxygen neutralization step during the de-chuck process in the via-etching process to release accumulated charges, combined with an argon de-chuck step to ensure complete charge neutralization, thereby reducing the JTAG failure rate without redesigning integrated circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If via-etching process is performed using electrostatic chuck, then etching precision is improved, but charge accumulation damage occurs causing high JTAG failure rates

Engineering Contradiction:

Improvevia-etching precisionVSAvoidJTAG failure rate

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by performing oxygen plasma treatment before the via-etching process to pre-neutralize charges on the wafer surface. This preventive measure reduces charge accumulation during etching, thereby lowering JTAG failure rates while maintaining etching precision through electrostatic chuck

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent converts the harmful effect of charge accumulation into a beneficial process by intentionally introducing oxygen plasma that generates controlled charges, which then neutralize the harmful charges accumulated during etching. This transforms the problematic charge buildup into a useful charge-neutralization mechanism

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

2Loss of time

If de-chuck step is performed without oxygen neutralization, then process time is reduced, but charge damage occurs to polysilicon and gate dielectrics

Engineering Contradiction:

Improveprocess timeVSAvoidcharge damage to polysilicon and gate dielectrics

Core Design Contradiction:

Loss of timeVSObject-affected harmful factors

Solution Approach 1:

The patent introduces oxygen plasma as an intermediary substance between the electrostatic chuck and the wafer during the de-chuck process. This intermediary layer neutralizes charges on the wafer surface, preventing direct charge discharge to the polysilicon and gate dielectrics when the wafer is released from the chuck

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Significantly reduces JTAG failure rates from 12-18% to less than 3%, ensuring lower discharging currents and minimizing damage to polysilicon and gate dielectrics by effectively neutralizing charges during the etching process.

Implementation Method 1

An oxygen neutralization step is performed during the de-chuck process in the via-etching process to release accumulated charges

Methodology Applied

Scientific EffectOxygen neutralization: Plasma

Implementation Method 2

placing the wafer on the ESC (electrostatic chuck)

Methodology Applied

Scientific EffectElectrostatic attraction: Electrostatics

Data Source

PatentUS8293649B2Release accumulative charges on wafers using O2 neutralization

Publication Date: 2012.10.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method of forming an integrated circuit structure on a wafer includes providing an etcher having an electrostatic chuck (ESC); and placing the wafer on the ESC. The wafer includes a conductive feature and a dielectric layer over the conductive feature. The method further includes forming and patterning a photo resist over the wafer; and etching the dielectric layer to form a via opening in the wafer using the etcher. An ashing is performed to the photo resist to remove the photo resist. An oxygen neutralization is performed to the wafer. A de-chuck step is performed to release the wafer from the ESC.