Oxygen-Scavenged Gate Stack for FinFET Leakage Control
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Solution Overview
Problem
As gate lengths in field-effect transistors decrease, short-channel effects and off-state leakage current increase, requiring a reduction in equivalent silicon oxide thickness (EOT) while maintaining low gate leakage current density, which is challenging with conventional high-k gate dielectrics like hafnium oxide.
Innovation Solution
The method involves oxygen scavenging to reduce the thickness of the interfacial layer in the gate dielectric stack, using a high-k gate dielectric and a scavenging metal layer to eliminate oxygen from the interfacial layer, thereby increasing the effective thickness of the silicon cap layer and reducing germanium segregation, while maintaining low interface state density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the physical thickness of the gate dielectric is reduced to decrease EOT, then short-channel effects are suppressed, but gate leakage current density increases
Solution Approach 1:
The gate dielectric is formed as a composite stack comprising an interfacial layer (such as SiO2 or SiON) and a high-k dielectric layer (such as HfO2, La2O3, or ZrO2). The interfacial layer provides good interface quality with the semiconductor substrate, while the high-k dielectric layer provides high permittivity to maintain gate capacitance with reduced physical thickness, thereby suppressing short-channel effects without excessive gate leakage.
Solution Approach 2:
The invention changes the dielectric permittivity parameter by introducing high-k materials (k > 20, preferably k > 25) into the gate dielectric stack. This allows the physical thickness of the gate dielectric to be reduced while maintaining the required gate capacitance density, thus suppressing short-channel effects while controlling gate leakage current density within acceptable limits.
2Reliability
If a high-k gate dielectric with k>25 is used to reduce EOT, then physical thickness can be increased for given gate capacitance, but interface state density may increase degrading carrier mobility
Solution Approach 1:
The gate dielectric is segmented into multiple functional layers: an interfacial layer in direct contact with the semiconductor substrate that ensures low interface state density, and a high-k dielectric layer that provides high permittivity. This segmentation allows each layer to optimize its specific function while working together to achieve low EOT and low interface state density simultaneously.
3Object-generated harmful factors
If oxygen is scavenged from the interfacial layer to reduce EOT, then gate leakage is suppressed, but germanium segregation may increase
Solution Approach 1:
A silicon cap layer is formed on the semiconductor fin surface before forming the interfacial layer. This preliminary silicon layer acts as a barrier that prevents germanium atoms from segregating to the surface during subsequent oxygen scavenging processes. The cap layer is later removed after the interfacial layer is formed, leaving a clean interface with reduced germanium segregation and low interface state density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses short-channel effects and reduces off-state leakage current while maintaining low gate leakage current density, improving the reliability and carrier mobility of the transistor.
Implementation Method 1
a scavenging metal layer is formed over the high-k gate dielectric. The scavenging metal layer has a first affinity for oxygen higher than a second affinity of a metal in the high-k gate dielectric and a third affinity of silicon. An anneal is performed to scavenge oxygen from at least a bottom portion of the silicon oxide layer to convert the bottom portion into a silicon layer
Data Source
AI summary
A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric.