Oxygen Termination Layer for Semiconductor Dielectric Interface

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Solution Overview

Problem

The increasing complexity of semiconductor manufacturing due to the scaling down of ICs, particularly the high interface trap density in compound semiconductor materials, which impairs the electrical performance and switching efficiency of integrated circuit devices, especially in high-frequency applications.

Innovation Solution

A method for forming a dielectric-semiconductor interface with reduced interface trap density by creating an oxygen termination layer on the semiconductor surface, followed by depositing a dielectric layer, which bonds with the semiconductor to reconstruct the crystalline lattice and minimize unsaturated bonds, thereby reducing interface trap density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If compound semiconductor materials are used to supplement or replace conventional silicon substrates, then electrical characteristics are improved, but interface trap density increases

Engineering Contradiction:
Improveelectrical characteristicsVSAvoidinterface trap density
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

A termination layer is introduced as an intermediary between the compound semiconductor material and the dielectric layer. This termination layer consists of a first layer of atoms from the compound semiconductor material and a second layer of oxygen atoms, which passivates the semiconductor surface and reduces interface trap density while maintaining the electrical characteristics of the compound semiconductor.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate stack employs a composite structure combining compound semiconductor material, termination layer with oxygen atoms, and dielectric layer. This composite approach leverages the superior electrical properties of compound semiconductors while using the termination layer to mitigate their inherent high interface trap density issue.

Inventive Principle:
Principle #40Composite materials

2Productivity

If geometry size is decreased to increase functional density, then production efficiency is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveproduction efficiencyVSAvoidmanufacturing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The termination layer is formed in advance before depositing the dielectric layer. This preliminary action prepares the semiconductor surface with proper termination (oxygen atoms) that reduces interface traps, ensuring optimal electrical performance is achieved before subsequent processing steps are performed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention changes the chemical composition and structure of the semiconductor surface by introducing a termination layer with specific atomic arrangements (first layer of semiconductor atoms, second layer of oxygen atoms). This parameter change in the interface structure reduces interface trap density and enables better performance at scaled dimensions.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly decreases interface trap density from approximately 10^13 defects/cm2 to around 10^11 defects/cm2, comparable to the benchmark of the Si/SiO2 interface, enhancing the electrical performance and switching efficiency of integrated circuit devices.

Implementation Method 1

depositing a dielectric layer, which bonds with the semiconductor to reconstruct the crystalline lattice and minimize unsaturated bonds

Methodology Applied
Scientific EffectChemical Bonding: Chemical Bonding

Implementation Method 2

depositing a dielectric layer above the termination layer, the depositing configured to not disrupt the termination layer

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Data Source

PatentUS9390913B2Semiconductor dielectric interface and gate stack
Publication Date: 2016.07.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9390913B2 patent drawing
  • US9390913B2 patent drawing
  • US9390913B2 patent drawing

AI summary

A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method comprises receiving a substrate, the substrate containing a semiconductor; preparing a surface of the substrate; forming a termination layer bonded to the semiconductor at the surface of the substrate; and depositing a dielectric layer above the termination layer, the depositing configured to not disrupt the termination layer. The forming of the termination layer may be configured to produce the termination layer having a single layer of oxygen atoms between the substrate and the dielectric layer.