P-Domino Register with Accelerated Non-Charge Path Timing
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Solution Overview
Problem
Traditional register circuits in pipeline systems introduce delays due to data-to-output time requirements, constraining the speed of complex logic circuits and limiting overall pipeline speed, especially in high leakage or high noise environments.
Innovation Solution
The development of non-inverting N-domino and P-domino registers with accelerated non-discharge or non-charge paths, utilizing pulsed clock signals and keeper paths to minimize hold time and enhance data-to-output speed without compromising stability, allowing for faster and smaller device implementation in high leakage or high noise processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional register circuits are used to hold outputs in pipeline stages, then data stability is ensured, but data-to-output time delays significantly reduce pipeline operating speed
Solution Approach 1:
The patent employs dynamic logic circuits (domino logic) that operate in two phases: precharge phase and evaluate phase. The precharge node dynamically switches between charged and discharged states based on clock signals, enabling the circuit to rapidly transition between stable states without requiring full traditional register setup and hold times. This dynamic operation reduces the data-to-output delay while maintaining data stability during the evaluation window.
Solution Approach 2:
The register circuit uses periodic clock signals to control the precharge and evaluate phases. The clock signal periodically resets the precharge node and enables evaluation windows, creating a rhythmic operation that ensures data stability during evaluation while minimizing the time required for data-to-output transition. This periodic action allows the circuit to achieve fast speed during the active evaluation phase while maintaining reliability through regular resetting.
2Reliability
If registers with strict setup and hold time requirements are used, then output stability is maintained, but the evaluation circuits in preceding stages are constrained and operate slower
Solution Approach 1:
The precharge node is precharged to a known state before the evaluation phase begins. This preliminary action prepares the circuit in advance, allowing the evaluation logic to operate without waiting for traditional register setup times. The precharge occurs during the clock high phase, and when the clock goes low, the evaluation window is immediately opened, enabling the evaluation circuit to operate at maximum speed without being constrained by setup time requirements.
Solution Approach 2:
The circuit transitions from a static register model with fixed setup and hold times to a dynamic domino logic model where the evaluation window is dynamically opened and closed by the clock signal. This dynamic approach allows evaluation circuits to operate as fast as their logic requires, with the precharge node dynamically switching states to maintain stability only when needed, thereby increasing overall productivity.
3Speed
If non-inverting domino registers are used to reduce clock-to-output time, then speed is improved, but hold time requirements remain and stability may be compromised in high leakage or high noise environments
Solution Approach 1:
The patent incorporates feedback paths that monitor the state of the precharge node and the output node. When the precharge node transitions state, the feedback mechanism ensures that the output stage is properly enabled or disabled to maintain stability. This feedback control allows the circuit to achieve fast clock-to-output times during evaluation while preventing instability caused by leakage or noise by only allowing output transitions when proper evaluation has occurred.
Solution Approach 2:
The circuit uses intermediate nodes and stages between the domino evaluation stage and the final output. These intermediary elements include the precharge node, output nodes, and enable logic that mediate between the fast-switching domino logic and the output buffer. This intermediary structure allows the fast domino logic to operate at high speed while the intermediaries filter out spurious transitions and maintain stability in high leakage or noise environments.
Data Source
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AI summary
A P-domino register has a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal. The pulsed clock signal lags a symmetric clock signal. The domino stage pre-discharges a pre-discharged node low when the symmetric clock signal is high and opens an evaluation window when the pulsed clock signal goes low, and pulls the pre-discharged node high if it evaluates, and keeps the pre-discharged node low if it fails to evaluate. The output stage provides an output signal based on states of the pre-discharged node and a second preliminary output node.