p-GaN HEMT Gate Bi-Layer for Low-Resistance Gate Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the manufacturing of III-N enhancement mode HEMT devices, there is a challenge in scaling down the gate length while maintaining low gate metal resistance and optimal device performance, particularly in achieving reduced threshold voltage and on-state gate leakage current, especially for low voltage applications.
Innovation Solution
A bi-layer metal structure is used, where a first metal layer forms a Schottky junction with a p-type doped GaN layer and is sandwiched between a second metal layer with lower sheet resistance, allowing for patterning and alignment to reduce total gate metal resistance while maintaining device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a single metal layer with limited thickness is used in the stacked gate patterning approach, then the device area can be scaled down with gate length reduced to 0.5 μm, but the gate metal resistance becomes too high
Solution Approach 1:
The gate metal structure is segmented into two distinct layers: a first metal layer (100 nm thick) that forms the Schottky junction with the p-GaN layer, and a second metal layer (500 nm thick) with lower sheet resistance that reduces overall gate resistance. This segmentation allows each layer to fulfill its specific function independently, resolving the contradiction between small area and low resistance.
Solution Approach 2:
The gate metal structure uses a composite bi-layer configuration combining two different metals with complementary properties. The first metal (e.g., TiN, TaN, or W) provides suitable Schottky junction characteristics, while the second metal (e.g., Al, Cu, or Ag) provides low sheet resistance. This composite approach enables simultaneous achievement of appropriate threshold voltage and low gate resistance in compact devices.
2Area of moving object
If the gate length is scaled down for compact devices, then the device area is reduced, but the gate metal resistance increases due to the smaller metal cross-section
Solution Approach 1:
Instead of relying solely on reducing gate length for area scaling, the invention adds a vertical dimension by stacking two metal layers. The second metal layer with lower sheet resistance compensates for the reduced horizontal dimensions, maintaining low gate resistance even as the device area is reduced to compact sizes.
Solution Approach 2:
The bi-layer metal structure uses composite materials with different electrical properties to overcome the resistance increase that would normally result from gate length scaling. The combination of two metals with complementary characteristics enables compact device dimensions while maintaining low gate resistance through the vertical stacking configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables gate length scaling and area scaling of the devices with improved gate reliability and performance characteristics, including reduced threshold voltage and on-state gate leakage current, suitable for low voltage applications and integration into GaN-integrated circuits.
Implementation Method 1
providing, on the p-type doped GaN layer, a metal layer, thereby forming a Schottky junction with the p-type doped GaN layer
Data Source
AI summary
A method includes providing a semiconductor structure including: a substrate; a layer stack with each layer of the layer stack including a Group III-nitride material; and a p-type doped GaN layer on the layer stack. The method also includes providing, on the GaN layer, a metal bi-layer including a first metal layer in contact with GaN layer and a second metal layer on the first metal layer and having a lower sheet resistance than the first metal layer. The method also includes performing a patterning process upon the metal bi-layer and the p-type doped GaN layer such that a first periphery of the first metal layer is aligned to a second periphery of the second metal layer and such that a first cross section of the metal bi-layer is smaller than a second cross section of the GaN layer parallel to the first cross section.