p-GaN HEMT Gate Passivation for Interface Reliability

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Solution Overview

Problem

Enhancement-mode high electron mobility transistors (HEMTs) with p-type doped GaN layers face issues with gate reliability and surface trapping, particularly in high voltage applications, due to weaknesses at the interface between the gate metal and p-type GaN, which prior passivation techniques have not adequately addressed.

Innovation Solution

A first passivation layer is sandwiched between the first metal electrode contact and the gate structure in the HEMT, using materials with ultra-wide bandgap and high-k properties such as AlN, InAlN, AlGaN, SiO2, Al2O3, SiN, HfO2, TiO2, or Ga2O3, or combinations thereof, to create an additional barrier against electron trapping and hole injection, thereby enhancing gate reliability and minimizing current collapse.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If prior passivation techniques are used to minimize surface trapping and device leakage, then surface trapping is reduced, but the interface between gate metal and p-type GaN remains a weak point allowing early onset of gate degradation

Engineering Contradiction:
Improvegate reliabilityVSAvoidinterface degradation
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

An AlN layer is introduced as an intermediary between the gate metal and the p-type GaN layer. This AlN interface layer acts as a mediator that prevents direct interaction between the metal and GaN, thereby eliminating the weak interface point and preventing gate degradation while maintaining effective passivation of the p-type GaN surface.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a passivation layer is added between gate metal and gate structure, then gate reliability improves, but device complexity increases

Engineering Contradiction:
Improvegate reliabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The AlN layer is applied locally only at the gate metal interface where it is most needed, rather than as a comprehensive structural modification throughout the device. This localized approach improves gate reliability by addressing the specific weak interface point without significantly increasing overall device complexity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The implementation of the passivation layer significantly improves gate reliability and reduces surface trapping, leading to improved electrical behavior and reduced gate leakage, with simulated results showing a 1-2 order of magnitude improvement in Ig@5V and no shift in Vth, ensuring the electrical behavior is unaffected by the presence of the passivation layer.

Implementation Method 1

Materials having ultra-wide bandgap and high-k properties such as AlN, InAlN and AlGaN, SiO2, Al2O3, SiN, HfO2, TiO2, or Ga2O3

Methodology Applied
Scientific EffectUltra-wide bandgap:

Implementation Method 2

Materials having ultra-wide bandgap and high-k properties such as AlN, InAlN and AlGaN, SiO2, Al2O3, SiN, HfO2, TiO2, or Ga2O3

Methodology Applied
Scientific EffectHigh-k dielectric property: Dielectric Permittivity

Implementation Method 3

it also minimizes electron trapping in the surface passivation and therefore suppresses current collapse

Methodology Applied
Scientific EffectElectron trapping:

Data Source

PatentUS11799000B1High electron mobility transistor and high electron mobility transistor forming method
Publication Date: 2023.10.24 HIPER SEMICONDUCTOR INC
  • US11799000B1 patent drawing
  • US11799000B1 patent drawing
  • US11799000B1 patent drawing

AI summary

A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor has a GaN epi-layer, a source ohmic contact, a drain ohmic contact, a gate structure, a first metal electrode contact and a first passivation layer. The source ohmic contact and the drain ohmic contact are disposed on the epi-layer. The gate structure is disposed on the epi-layer and between the source ohmic contact and the drain ohmic contact. The first metal electrode contact is disposed above the gate structure. The first passivation layer is sandwiched between the first metal electrode contact and the gate structure.