P-Type Gate GaN FET Structure for Low-Threshold Cascode Switching
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Solution Overview
Problem
Normally-on gallium nitride field effect transistors (GaN FETs) are not suitable for power switching applications, as they require larger silicon transistors and higher costs due to high threshold voltage, making normally-off operation challenging.
Innovation Solution
A gallium nitride based low threshold depletion mode transistor with a channel layer of III-N semiconductor material, a barrier layer of aluminum and nitrogen, and a p-type gate of gallium and nitrogen, without a dielectric layer between the gate and the barrier layer, is developed, achieving a threshold potential between −10 volts and −0.1 volts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a normally-on GaN FET with high threshold voltage is used, then gate leakage is reduced and product reliability is ensured, but the size and cost of silicon transistors increase
Solution Approach 1:
The patent changes the threshold voltage parameter of the GaN FET from high (above 10V) to low (between -10V and -0.1V) by modifying the gate structure. Specifically, it uses a p-type gate made of III-N semiconductor material without a dielectric layer, which fundamentally alters the electrical characteristics and enables low threshold voltage operation while maintaining reliability
Solution Approach 2:
The patent extracts and removes the dielectric layer that is traditionally present between the gate and barrier layer in conventional GaN FETs. This removal eliminates the high threshold voltage characteristic and enables the transistor to operate with low threshold voltage, thereby reducing the size requirements for paired silicon transistors
2Reliability
If a normally-on GaN FET with high threshold voltage is used, then gate leakage is reduced, but the cost increases
Solution Approach 1:
The patent changes the threshold voltage parameter to low values through structural modification (p-type gate without dielectric layer), which reduces the specifications required for paired silicon transistors. This parameter change leads to smaller, cheaper silicon transistors can be used, thereby reducing overall manufacturing cost while maintaining gate leakage performance
Solution Approach 2:
By enabling low threshold voltage operation, the patent allows the use of smaller, less expensive silicon transistors in cascode configurations. These cheaper silicon transistors can be used effectively without requiring the large, costly transistors that would be needed for high threshold voltage GaN FETs
3Reliability
If a normally-on GaN FET with high threshold voltage is used, then gate leakage is reduced, but the on-resistance increases
Solution Approach 1:
The patent changes the threshold voltage parameter to low values through the p-type gate structure without dielectric layer. This parameter change enables the use of smaller silicon transistors with lower on-resistance in paired configurations, thereby reducing overall on-resistance and energy loss while maintaining gate leakage performance
4Reliability
If a normally-on GaN FET with high threshold voltage is used, then gate leakage is reduced, but the available space decreases
Solution Approach 1:
The patent changes the threshold voltage parameter to low values, which reduces the size requirements for paired silicon transistors. This frees up space within the package that can then be allocated to the GaN transistor itself, increasing the available space for the GaN device while maintaining gate leakage performance
Data Source
AI summary
A semiconductor device includes a gallium nitride based low threshold depletion mode transistor (GaN FET) with a threshold potential between −10 volts and −0.5 volts. The GaN FET has a channel layer of III-N semiconductor material including gallium and nitrogen that supports a two-dimensional electron gas (2DEG). The GaN FET has a barrier layer of III-N semiconductor material including aluminum and nitrogen over the channel layer. The GaN FET further has a p-type gate of III-N semiconductor material including gallium and nitrogen. A bottom surface of the gate, adjacent to the barrier layer, does not extend past a top surface of the barrier layer, located opposite from the channel layer. The GaN FET is free of a dielectric layer between the gate and the barrier layer.