P-Type Gate GaN FET Structure for Lower Cascode Threshold Voltage
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Solution Overview
Problem
Normally-on gallium nitride field effect transistors (GaN FETs) are not suitable for power switching applications as they require larger silicon transistors and higher costs due to high threshold voltage, making normally-off operation challenging.
Innovation Solution
A gallium nitride based low threshold depletion mode transistor is developed with a channel layer of III-N semiconductor material, a barrier layer of aluminum and nitrogen, and a p-type gate of gallium and nitrogen, eliminating the dielectric layer between the gate and barrier layer, which reduces the threshold potential to between −10 volts and −0.1 volts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dielectric layer is used between the gate and barrier layer in normally-on GaN FET, then gate leakage is reduced and product reliability is ensured, but threshold voltage magnitude increases above 10 volts requiring larger silicon transistors
Solution Approach 1:
The patent removes the dielectric layer between the gate and barrier layer, extracting the component that was causing high threshold voltage. This elimination allows the threshold voltage to be reduced to below 10 volts in magnitude, enabling the use of smaller silicon transistors while maintaining gate leakage control through alternative means such as the p-type gate structure and barrier layer composition.
2Ease of operation
If the threshold voltage magnitude of normally-on GaN FET is high, then gate control is improved, but silicon transistor size increases leading to higher costs and increased on-resistance
Solution Approach 1:
The patent changes key parameters including the gate material composition (p-type III-N semiconductor), barrier layer composition (AlGaN with specific aluminum content), and eliminates the dielectric layer. These parameter changes collectively reduce the threshold voltage magnitude to below 10 volts while maintaining effective gate control through the engineered p-type gate structure and heterojunction properties.
3Ease of operation
If a cascode circuit with normally-on GaN FET and silicon transistor is used, then normally-off operation is achieved, but overall on-resistance increases and available space decreases
Solution Approach 1:
By removing the dielectric layer and reconfiguring the gate structure to p-type III-N semiconductor, the patent reduces the threshold voltage requirement. This extraction of the problematic dielectric component allows the silicon transistor in the cascode circuit to be smaller, thereby reducing its on-resistance contribution and freeing up space within the package while maintaining normally-off operation capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables a smaller size for silicon transistors, reduces on-resistance, and lowers costs by allowing for normally-off operation with a lower threshold voltage, improving the efficiency and cost-effectiveness of power switching applications.
Implementation Method 1
a channel layer of III-N semiconductor material including gallium and nitrogen that supports a two-dimensional electron layer, commonly referred to as the two-dimensional electron gas (2DEG)
Data Source
AI summary
A semiconductor device includes a gallium nitride based low threshold depletion mode transistor (GaN FET) with a threshold potential between −10 volts and −0.5 volts. The GaN FET has a channel layer of III-N semiconductor material including gallium and nitrogen that supports a two-dimensional electron gas (2DEG). The GaN FET has a barrier layer of III-N semiconductor material including aluminum and nitrogen over the channel layer. The GaN FET further has a p-type gate of III-N semiconductor material including gallium and nitrogen. A bottom surface of the gate, adjacent to the barrier layer, does not extend past a top surface of the barrier layer, located opposite from the channel layer. The GaN FET is free of a dielectric layer between the gate and the barrier layer.