P-Type Gate HEMT Layer Structure for Lower Gate Leakage
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Solution Overview
Problem
P-type gate HEMT devices suffer from high gate leakage current and low stability, which are not adequately addressed by existing enhancement mode devices.
Innovation Solution
A semiconductor structure with a P-type semiconductor layer comprising a non-activated layer and an activated layer, where the non-activated layer is located close to the substrate, and an N-type doped layer is introduced to form a PN junction, reducing gate leakage current and enhancing device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a P-type semiconductor layer is used to deplete the two-dimensional electron gas at the gate, then the device achieves enhancement mode operation and normally-off state, but the gate leakage current increases and device stability decreases
Solution Approach 1:
The P-type semiconductor layer is segmented into multiple regions with different doping concentrations: a first P-type region with higher doping concentration and a second P-type region with lower doping concentration. This segmentation allows the first region to provide strong depletion capability for enhancement mode operation, while the second region reduces gate leakage current, thereby resolving the contradiction between achieving normally-off state and reducing leakage.
Solution Approach 2:
Different regions of the P-type semiconductor layer are assigned different doping concentrations to perform different functions. The first P-type region (higher doping) is optimized for depletion capability at the gate, while the second P-type region (lower doping) is optimized for reducing gate leakage. This local quality differentiation resolves the contradiction by optimizing each region for its specific function rather than using a uniform doping concentration throughout.
2Reliability
If a P-type gate HEMT device is designed for enhancement mode operation, then failure protection is improved, but output current density decreases
Solution Approach 1:
The P-type semiconductor layer is divided into first and second P-type regions with different doping concentrations. The first region provides strong depletion for enhancement mode operation (improving failure protection), while the second region with lower doping maintains better electrical characteristics for output current density, thus resolving the contradiction between failure protection and output performance.
Solution Approach 2:
The doping concentration parameter is changed across different regions of the P-type semiconductor layer. By varying the doping concentration from high in the first region to low in the second region, the device achieves both enhancement mode operation (for failure protection) and maintains adequate output current density, resolving the contradiction through parameter optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces gate leakage current and improves the reliability of the P-type gate HEMT device by ensuring a normally-off state and minimizing the impact of surface states on channel conduction.
Implementation Method 1
an N-type doped layer and an activated layer which are stacked sequentially, the non-activated layer is located on a side, close to the substrate, of the P-type semiconductor layer
Data Source
AI summary
A semiconductor structure includes a substrate, a channel layer and a barrier layer which are stacked sequentially, the channel layer and the barrier layer including a gate region, a source region located at one side of the gate region and a drain region located at another one side of the gate region; and a P-type semiconductor layer, located at least in the gate region and located at a side, away from the substrate, of the barrier layer; where the P-type semiconductor layer includes a non-activated layer, an N-type doped layer and an activated layer which are stacked sequentially, and the non-activated layer is located on a side, close to the substrate, of the P-type semiconductor layer.