P+ Guard Ring Layout for SEL Mitigation in ICs
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Solution Overview
Problem
Single event latch-up (SEL) in semiconductor structures of integrated circuits leads to abnormal high-current states, potentially damaging the device by causing heat generation and metal migration, which existing technologies have not adequately addressed.
Innovation Solution
A p-type device-centric approach is implemented, where a p+ guard ring is formed around p-type devices or clusters of p-type devices, with an n+ guard ring inside and an additional n+ guard ring between the n+ and p+ guard rings, reducing the likelihood of latch-up by decoupling parasitic bipolar junctions and minimizing the layout size and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SEL mitigation techniques are used with multiple guard rings around both p-type and n-type devices, then SEL protection is improved, but device complexity and layout size increase
Solution Approach 1:
The patent applies local quality by placing guard rings selectively only around p-type devices rather than uniformly around all devices. This is achieved through the method of forming a p-type well in an n-type substrate, forming p-type devices in the p-type well, and then forming guard rings around selected p-type devices. This selective approach maintains SEL protection where most needed while reducing overall complexity and layout size.
Solution Approach 2:
The patent extracts the guard ring protection mechanism from being a universal requirement for all devices and applies it only where necessary - specifically around p-type devices. By removing the unnecessary guard rings around n-type devices, the patent reduces layout complexity while maintaining adequate SEL mitigation through the p-type device-centric approach.
2Reliability
If multiple guard rings are placed around all devices, then SEL protection is improved, but manufacturing process complexity increases
Solution Approach 1:
The manufacturing process implements local quality by configuring guard rings only around p-type devices during fabrication. The process involves forming a p-type well in an n-type substrate, creating p-type devices within the well, and then selectively forming guard rings around these p-type devices. This localized approach simplifies the manufacturing process compared to uniformly protecting all devices while maintaining effective SEL mitigation.
3Reliability
If larger layout size is used to accommodate multiple guard rings, then SEL protection is improved, but area utilization decreases
Solution Approach 1:
The patent extracts unnecessary guard ring structures from the layout by removing them around n-type devices. By maintaining guard rings only around p-type devices in the p-type well structure, the patent reduces the total layout area occupied by guard rings while preserving SEL protection effectiveness. This extraction of redundant elements optimizes area utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively mitigates SEL by reducing the gain of parasitic SCR structures, preventing continuous current flow and thus protecting the integrated circuit from damage, while simplifying the design and reducing unnecessary guard rings.
Implementation Method 1
reducing the likelihood of latch-up by decoupling parasitic bipolar junctions and minimizing the layout size and complexity
Data Source
AI summary
Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a semiconductor structure includes a semiconductor substrate, a p-type transistor having p+ source/drain regions disposed in a n-doped region in the semiconductor substrate, an n-type transistor having n+ source/drain regions disposed in a p-doped region in the semiconductor substrate, a n+ guard ring disposed in the n-doped region and laterally around the p+ source/drain regions of the p-type transistor, and a p+ guard ring disposed laterally around the n-doped region. The p+ guard ring is disposed between the p-type transistor and the n-type transistor.