P-Type Access SRAM Cells with CFET Vertical Stacking
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Solution Overview
Problem
SRAM faces scalability issues due to lithography challenges associated with process scaling, particularly in the non-scalability of routing resources for cross-coupled nodes and connections between bit-cells and bit lines, leading to a disparity in scaling between logic and memory devices.
Innovation Solution
Implementing pMOS access transistors in SRAM cells and leveraging CFET technology to vertically integrate pMOS and nMOS transistors, optimizing interconnects and back-end technologies to achieve 50% area scaling, and utilizing P-SRAM or P-cell technology to eliminate non-scaling issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional nMOS access transistors are used in SRAM cells, then the routing resources for cross-coupled nodes and bit line connections can be scaled, but lithography challenges prevent scalability at advanced process nodes
Solution Approach 1:
The patent transitions from planar 2D transistor layout to 3D vertical stacking architecture. By stacking nMOS and pMOS transistors vertically in CFET structures, the design achieves area reduction while maintaining routing scalability, effectively adding a vertical dimension to overcome lithography limitations at advanced process nodes
2Area of stationary object
If SRAM cell area is reduced to improve density, then more cells can be integrated, but routing resources for cross-coupled nodes and bit line connections become non-scalable
Solution Approach 1:
By implementing vertical stacking of transistors and interconnects in the third dimension, the patent reduces planar footprint while preserving routing scalability. The vertical architecture allows cross-coupled nodes and bit line connections to be routed through multiple layers without consuming excessive planar area, thus maintaining adaptability as cell size shrinks
Solution Approach 2:
The patent employs nested interconnect structures where lower metal layers are positioned beneath upper metal layers in the vertical stack. This nesting allows multiple routing resources to be packed into a compact vertical footprint, enabling both area reduction and routing scalability to coexist
3Area of stationary object
If vertical stacking of nMOS and pMOS transistors is implemented using CFET technology, then area scaling is achieved, but device complexity increases
Solution Approach 1:
The patent merges nMOS and pMOS transistors into unified vertical CFET stacks, where complementary transistors share common diffusion regions and interconnect structures. This merging reduces the number of discrete components and interconnections required, thereby achieving area scaling while managing device complexity through integration
Data Source
AI summary
Embodiments herein relate to scaling of Static Random Access Memory (SRAM) cells. An SRAM cell include nMOS transistors on one level above pMOS transistors on a lower level. Transistors on the two levels can have overlapping footprints to save space. Additionally, the SRAM cell can use pMOS access transistors in place of nMOS access transistors to allow reuse of areas of the cell which would otherwise be used by the nMOS access transistors. In one approach, gate interconnects are provided in these areas, which have an overlapping footprint with underlying pMOS access transistors to save space. The SRAM cells can be connected to bit lines and word lines in overhead and/or bottom metal layers. In another aspect, SRAM cells of a column are connected to bit lines in an overlying M0 metal layer and an underlying BM0 metal layers to reduce capacitance.