P-Type Dopant Gate Electrode Silicidation for Transient Stress Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for manufacturing silicided metal gate structures face challenges such as incomplete polysilicon reaction and metal penetration into the channel, leading to transient stress and potential device failure, particularly due to the formation of high-stress transient silicide phases during the silicidation process.
Innovation Solution
Incorporating a p-type dopant, such as boron, into the gate electrode material before or during the silicidation process to reduce or eliminate the formation of transient phases like Ni31Si12, thereby minimizing transient stress and ensuring complete silicidation without metal penetration into the channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a mild anneal is used to form the silicide, then the gate electrodes will fully react, but the silicidation will be incomplete
Solution Approach 1:
The patent introduces dopant concentration as a new parameter to control the silicidation process. By adjusting the dopant type and concentration in the polysilicon gate electrode, the reaction kinetics are modified to achieve complete consumption of polysilicon at lower anneal temperatures, preventing metal penetration while ensuring full reaction.
Solution Approach 2:
The dopant acts as an intermediary that facilitates the reaction between metal and polysilicon. Specifically, dopants like phosphorus or boron modify the polysilicon structure to enhance metal diffusion and reaction rate, enabling complete silicidation under milder conditions that prevent catastrophic metal penetration into the channel.
2Manufacturing precision
If an aggressive anneal is used to form the silicide, then the silicidation will be complete, but the metal will penetrate into the channel
Solution Approach 1:
The patent changes the temperature parameter of the anneal process by using dopant-assisted silicidation. The presence of dopants enables complete polysilicon consumption at lower temperatures (e.g., 400-600°C instead of 700-900°C), thereby achieving complete silicidation without the aggressive heating that causes metal penetration into the channel.
Solution Approach 2:
The dopant serves as a mediator that accelerates the silicidation reaction kinetics. By incorporating dopants like phosphorus or boron into the polysilicon gate electrode before metal deposition, the reaction proceeds rapidly at lower temperatures, completing the silicidation before metal atoms can diffuse into the channel region.
3Ease of manufacture
If conventional silicidation is used, then the process is simple, but transient stress causes high-stress transient silicide phases to form
Solution Approach 1:
The patent modifies the compositional parameter of the polysilicon gate electrode by adding dopants. This compositional change alters the phase transformation behavior during silicidation, suppressing the formation of high-stress transient silicide phases like Ni3Si2 and promoting direct formation of low-stress final phases like NiSi, thereby reducing transient stress while maintaining process simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of p-type dopants in the silicidation process effectively reduces transient stress, ensuring fully silicided gate electrodes with reduced risk of metal penetration, thereby enhancing the reliability and performance of semiconductor devices.
Implementation Method 1
siliciding the gate electrode to form a silicided gate electrode
Implementation Method 2
placing a p-type dopant within the layer of gate electrode material or the NMOS gate electrode prior to or concurrently with siliciding
Data Source
AI summary
The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming a layer of gate electrode material over a layer of gate dielectric material, wherein the layer of gate dielectric material is positioned over a substrate (210). This method further includes patterning the layer of gate electrode material and the layer of gate dielectric material into an NMOS gate structure (230), wherein the NMOS gate structure (230) includes an NMOS gate dielectric (240) and an NMOS gate electrode (250). This method further includes forming n-type source/drain regions (710) within the substrate (210) proximate the NMOS gate structure (230), and siliciding the NMOS gate electrode (250) to form a silicided gate electrode (1110, 1210). This method additionally includes placing a p-type dopant within the layer of gate electrode material or the NMOS gate electrode (250) prior to or concurrently with siliciding.