P-type Metal Gate Uniformity via Segmented Dummy Gate Replacement
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Solution Overview
Problem
The integration of processes and materials for forming metal gate stacks in semiconductor devices, particularly for n-type and p-type MOS transistors, leads to issues such as damage and non-uniformity of the p-type metal gate during polysilicon removal, resulting in high resistance and performance variation.
Innovation Solution
A method involving the formation of high k dielectric and polysilicon layers, followed by patterning and chemical mechanical polishing (CMP) processes to create dummy gates, which are then replaced with metal gates of specific work functions, ensuring uniformity and integrity of the p-type metal gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a polysilicon removal process is applied to form an n-type metal gate, then the n-type metal gate can be formed, but the p-type metal gate is damaged and recessed causing high resistance
Solution Approach 1:
The patent divides the gate formation process into separate sequential steps for p-type and n-type gates. The p-type metal gate is formed and processed first, then protected during subsequent n-type metal gate formation. This segmentation prevents the polysilicon removal process from damaging the p-type gate, resolving the contradiction between forming the n-type gate and maintaining p-type gate integrity.
Solution Approach 2:
The p-type metal gate is formed and planarized using CMP before the n-type metal gate formation process begins. This preliminary action ensures the p-type gate is already in its final state and protected from subsequent processing steps that would otherwise damage it, thereby maintaining low resistance while enabling n-type gate formation.
2Productivity
If the p-type metal gate is exposed to polysilicon removal process, then the n-type metal gate can be formed, but the p-type metal gate becomes non-uniform causing device performance variation
Solution Approach 1:
The patent segments the dual-gate formation into distinct process modules: first forming and planarizing the p-type metal gate, then separately forming the n-type metal gate. This segmentation allows each gate type to be optimized independently, maintaining uniformity while achieving integrated circuit productivity.
Solution Approach 2:
The patent uses an intermediary protection layer or masking approach during the n-type gate formation to protect the already-formed p-type gate. This intermediary measure prevents the polysilicon removal process from affecting the p-type gate, maintaining its uniformity while still enabling the n-type gate to be formed through the same process sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the uniformity and integrity of p-type metal gate electrodes, reducing resistance and improving device performance by avoiding damage during polysilicon removal and maintaining the expected work function, thereby improving circuit performance and reducing RC delay.
Implementation Method 1
applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate, exposing the first and the second dummy gates
Data Source
AI summary
The present disclosure provides a method that includes forming a high k dielectric layer on a semiconductor substrate; forming a polysilicon layer on the high k dielectric layer; patterning the high k dielectric layer and polysilicon layer to form first and second dummy gates in first and second field effect transistor (FET) regions, respectively; forming an inter-level dielectric (ILD); applying a first CMP process to the semiconductor substrate, exposing the first and second dummy gates; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a first metal electrode in the first gate trench; applying a second CMP process; forming a mask covering the first FET region and exposing the second dummy gate; thereafter removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a second metal electrode in the second gate trench; and applying a third CMP process.