P-Type SiGe Epitaxy With Ga-In-B Doping for Low Contact Resistance
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Solution Overview
Problem
Conventional methods face challenges in achieving high boron solubility in silicon germanium films for p-type MOS devices, leading to high contact resistance issues due to low boron solubility in germanium, and existing techniques like high-temperature annealing can cause dopant clustering, limiting the reduction of contact resistivity in silicon germanium layers.
Innovation Solution
A method involving the use of boron, gallium, and indium as p-type dopant precursors in a chemical vapor deposition process at lower temperatures to form epitaxial p-type doped silicon germanium layers, with specific precursor formulations and conditions that reduce carbon incorporation and enhance gallium incorporation, thereby lowering contact resistance without the need for high-temperature annealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high boron concentration is used in silicon germanium film to reduce contact resistance, then contact resistivity decreases, but boron solubility limits prevent achieving sufficiently high concentrations
Solution Approach 1:
The patent changes the physical state and delivery method of boron by using boron-containing precursors in chemical vapor deposition. Instead of attempting to incorporate solid boron directly into the film, the process uses gaseous precursors (such as diborane or boron halides) that can be delivered in controlled amounts during epitaxial growth, enabling higher effective boron concentrations to be achieved while remaining within solubility limits.
Solution Approach 2:
The patent introduces chemical precursors as intermediaries to deliver boron to the silicon germanium film. These precursors (e.g., B2H6, BF3, BCl3) act as carriers that facilitate boron incorporation during the CVD process, overcoming the direct solubility limitation by controlling delivery rate and reaction conditions during film formation.
2Reliability
If high-temperature annealing is used to increase dopant solubility and reduce contact resistance, then dopant concentration increases, but dopant clustering occurs at the surface
Solution Approach 1:
The patent performs dopant incorporation during the epitaxial growth process itself, before any annealing step is required. By incorporating boron during low-temperature CVD growth, the dopant is uniformly distributed throughout the film matrix from the beginning, eliminating the need for subsequent high-temperature annealing that would cause clustering. The doping action is completed preliminarily during growth.
Solution Approach 2:
The patent replaces the thermal diffusion mechanism (annealing) with a chemical incorporation mechanism (CVD). Instead of using heat to drive dopant diffusion into the film, the process uses chemical reactions during growth to incorporate boron uniformly throughout the film, substituting a chemical growth process for a thermal diffusion process and avoiding the clustering associated with high-temperature treatment.
3Speed
If conventional scaling techniques are used to improve device speed and density, then device performance increases, but challenges arise for future technology nodes
Solution Approach 1:
The patent changes the material parameters of the source/drain regions by forming silicon germanium alloys with specific germanium concentrations (e.g., 30-70% Ge). This material composition change enables strain engineering that enhances carrier mobility without requiring further dimensional scaling, providing a new parameter (material composition) to optimize device performance as conventional scaling approaches its limits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively forms p-type doped silicon germanium layers with low contact resistance and high mobility, suitable for use in FinFETs and GAA FETs, while maintaining structural integrity and reducing channeling effects, enabling improved performance in semiconductor devices.
Implementation Method 1
providing a silicon precursor to the reaction chamber, providing a germanium precursor to the reaction chamber, and providing one or more p-type dopant precursors to the reaction chamber
Implementation Method 2
forming the p-type doped silicon germanium layer by providing a silicon precursor to the reaction chamber, providing a germanium precursor to the reaction chamber
Data Source
AI summary
Methods and systems for forming a p-type doped silicon germanium layer. The p-type doped silicon germanium layer can include silicon, germanium, gallium, and, in at least some cases, indium.