P2P I/O Address Filters for CPU-Free Peer Validation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing peer-to-peer (P2P) communication between I/O devices in computers relies on central processing unit (CPU) address validation, which is inefficient and power-hungry, and existing address translation services (ATS) suffer from performance bottlenecks due to limited cache coverage and frequent revalidation.
Innovation Solution
Implementing a method that identifies isolation groups within a virtual partitioning of I/O device address space and stores address filters at I/O devices or switch ports, allowing direct P2P communication without CPU intervention, thus preventing unauthorized access and avoiding the use of address translation caches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CPU performs address validation for P2P communication, then address validation is achieved, but CPU involvement increases power consumption and reduces efficiency
Solution Approach 1:
The patent extracts the address validation function from the CPU and implements it locally at the I/O device through address filters. This removes the burden of CPU involvement in P2P communication address validation, reducing power consumption while maintaining validation reliability.
Solution Approach 2:
The I/O device performs address validation for itself using locally stored address filters, eliminating the need for external CPU intervention. This self-service approach reduces power consumption and improves efficiency by handling validation autonomously at the device level.
2Speed
If ATS caches validated DMA addresses in I/O devices, then P2P communication speed is improved, but limited cache coverage causes frequent revalidation and performance bottlenecks
Solution Approach 1:
The patent segments the address validation mechanism into isolation groups, where each group maintains address filters for specific peer devices. This segmentation allows broader coverage without requiring a large centralized cache, eliminating the performance bottleneck while maintaining high communication speed.
Solution Approach 2:
Instead of relying on a limited cache structure, the patent introduces address filters organized by isolation groups, creating a new dimensional approach to address validation. This filter-based system provides extensive coverage without the revalidation overhead that plagues cache-based systems.
3Measurement precision
If address filters are stored at I/O devices, then address validation granularity is improved, but device memory requirements increase
Solution Approach 1:
The patent divides the address validation data structure into isolation groups, with each group maintaining filters only for its member devices. This segmentation reduces the total memory requirement compared to a comprehensive cache, while still providing fine-grained address validation precision through the filter mechanism.
Data Source
AI summary
Address validation for peer-to-peer communication among a plurality of I/O devices via an interconnect includes identifying a number of isolation groups within a virtual partitioning of address space of the I/O devices; and storing address filters at locations associated with the plurality of I/O devices. Let N be the number of isolation groups, and i be an index from 1 to N. Each isolation group includes a subset of the plurality of I/O devices. The address filter associated with an I/O device of an ith isolation group includes identifications and address ranges of other I/O devices of the ith isolation group so as to authorize read and write operations on peer address space of the ith isolation group.