P4 Switch Packet Aggregation via Ring Buffer

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Solution Overview

Problem

Current packet aggregation methods are inefficient due to high network bandwidth wastage from large packet headers and limitations in handling packets of varying lengths, and traditional CPU-based solutions perform poorly in real-world network scenarios.

Innovation Solution

A packet aggregation method for a P4 switch that parses and stores message headers in a ring buffer, allowing for the creation of aggregated packets without length or number limitations, using flag headers to manage data recirculation and output, and a corresponding disaggregation method to restore original packets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional CPU-based packet aggregation is used, then packet aggregation function can be implemented, but processing performance is very low

Engineering Contradiction:
Improvepacket aggregation performanceVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces the traditional CPU-based software processing mechanism with a P4 switch hardware-based processing mechanism. The P4 switch uses programmable data plane processors to perform packet parsing, matching, and aggregation in hardware, substituting the mechanical CPU execution model with a specialized hardware architecture that achieves line-rate performance while reducing system complexity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces a ring buffer as an intermediary data structure between packet reception and aggregation output. The ring buffer temporarily stores parsed message headers and coordinates the timing between packet arrival and aggregation completion, enabling efficient data flow management without blocking the high-performance hardware processing pipeline.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If packet aggregation is implemented in switch with previous technologies, then aggregation function is achieved, but only fixed-length packets can be aggregated and packet number is limited

Engineering Contradiction:
Improvepacket length adaptabilityVSAvoidaggregation control complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic packet aggregation where the aggregation parameters (packet length, packet number) are not fixed but adapt based on the actual traffic flow characteristics. The P4 switch dynamically adjusts aggregation behavior by parsing variable-length packets, matching based on flow identifiers, and flexibly determining when aggregation thresholds are met, enabling adaptation to diverse packet sizes and rates without complex external control.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the aggregation parameters dynamically based on traffic conditions. Instead of fixed packet lengths and predetermined aggregation counts, the system monitors incoming packet characteristics and adjusts aggregation behavior in real-time, allowing the same aggregation mechanism to handle both small IoT packets and larger data packets efficiently.

Inventive Principle:
Principle #35Parameter changes

3Loss of energy

If IoT small packets are transmitted individually, then each packet can be transmitted independently, but network bandwidth is wasted on packet headers

Engineering Contradiction:
Improvenetwork bandwidth wastageVSAvoidpacket processing complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent merges multiple small IoT packets into a single aggregated packet by combining their message headers while sharing common protocol headers (Ethernet, IP, UDP). This merging approach eliminates redundant header transmissions, reducing network bandwidth consumption from 72% header overhead to approximately 10% in aggregated form, while the P4 switch handles the merging process efficiently in hardware.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11343360B2Packet aggregation and disaggregation method
Publication Date: 2022.05.24 NAT CHIAO TUNG UNIV
  • US11343360B2 patent drawing
  • US11343360B2 patent drawing
  • US11343360B2 patent drawing

AI summary

The present disclosure provides packet aggregation and disaggregation methods. In the packet aggregation methods, the protocol-independent packet processor (P4) switch stores plural message headers of plural packets in the ring buffer. When the plural message headers stored in the ring buffer reach a pre-defined amount of data, the P4 switch replaces the first flag header in the current packet with a second flag header so as to form a work packet. The egress pipeline of the P4 switch recirculates the work packet repeatedly, whenever it receives a work packet, a message header is extracted from a plurality of message headers in the ring buffer and added to the working packet for packet aggregation.