Power Amplifier Ground Layout With Parallel Paths for Low Noise

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Solution Overview

Problem

Power amplifier modules in mobile phone frontend circuits experience increased power noise due to inductance components generated by wiring lines connecting amplifier elements to the ground layer on multilayer substrates, which affects signal transmission and reception.

Innovation Solution

The power amplifier module incorporates conductive patterns formed between amplifier elements and the ground pattern layer, with these patterns connected in parallel to reduce the inductance component, thereby minimizing power noise. Additional conductive patterns can be formed in different layers to enhance flexibility and adjust impedance, specifically connecting the first and third conductive patterns closer to the amplifier elements than the ground layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wiring lines connect amplifier elements to ground layer on multilayer substrate, then electrical connection is established, but inductance component increases causing power noise

Engineering Contradiction:
Improvepower noiseVSAvoidinductance component
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The ground connection path is segmented into multiple parallel conductive patterns instead of a single wiring line. This divides the current path into multiple segments that can carry current simultaneously, reducing the overall inductance and minimizing power noise while maintaining reliable electrical connection.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple conductive patterns are merged in parallel to form a composite ground connection path. By combining multiple low-inductance paths, the overall inductance is reduced and current distribution is improved, thereby reducing power noise without compromising connection reliability.

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If conductive patterns are formed in multiple layers, then flexibility and impedance adjustment are enhanced, but device complexity increases

Engineering Contradiction:
Improveimpedance adjustmentVSAvoidconductive pattern configuration
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The ground connection is extended from a two-dimensional planar layout to a three-dimensional multilayer structure. Conductive patterns are distributed across multiple substrate layers, providing additional spatial dimensions for impedance control and current distribution, thereby enhancing adaptability while managing complexity through systematic layer utilization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces power noise by minimizing inductance components between amplifier elements and the ground layer, improving signal transmission and reception quality in mobile phone frontend circuits.

Implementation Method 1

an inductance component is generated in a grounded part of a power amplifier element due to a wiring line that connects an amplifier and a ground layer formed in the multilayer substrate to each other

Methodology Applied
Scientific EffectInductance: Inductor

Implementation Method 2

a first bypass capacitor that has one end connected to the third terminal

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS11870401B2Power amplifier module, frontend circuit, and communication device
Publication Date: 2024.01.09 MURATA MFG CO LTD
  • US11870401B2 patent drawing
  • US11870401B2 patent drawing
  • US11870401B2 patent drawing

AI summary

A PA module includes: a multilayer substrate having a ground pattern layer connected to a ground of a power source; amplifier transistors disposed on the multilayer substrate; a bypass capacitor having one end connected to the collector of the amplifier transistor; a first wiring line connecting the emitter of the amplifier transistor and the ground pattern layer to each other; a second wiring line connecting the emitter of the amplifier transistor and the ground pattern layer to each other; a third wiring line connecting the other end of the bypass capacitor and the ground pattern layer to each other; and a fourth wiring line formed between the amplifier transistor and the ground pattern layer and between the bypass capacitor and the ground pattern layer and connecting the first wiring line and the third wiring line to each other.