Pack-Insert Signal Processing for Byte Mapping at 4G Data Rates
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Solution Overview
Problem
Conventional signal processing devices face performance issues in implementing byte to any byte mapping operations required for 4G mobile telecommunications due to complex control settings and the need for multiple instructions, which are inefficient for high data rates.
Innovation Solution
A signal processing device and method that utilize a pack-insert instruction to combine data block insertion and packing into a single operation, reducing the number of instructions needed and enabling the use of wide load and store instructions, thereby improving performance for operations like interleaving and de-interleaving.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional pack, insert-extract and permute instructions are used for byte to any byte mapping, then the operation can be completed, but the number of instructions and cycles required is large, leading to poor performance for 4G data rates
Solution Approach 1:
The patent combines the pack instruction and insert-extract instruction into a single unified pack-insert instruction. This merging eliminates the need to execute separate instructions for packing data blocks and inserting them at specific positions, thereby reducing the total number of instructions and execution cycles while improving processing throughput for 4G applications
2Adaptability or versatility
If a butterfly and reverse butterfly schematic is used for any byte to any byte mapping, then the mapping operation can be implemented, but the implementation becomes complicated with multiple stages and control settings
Solution Approach 1:
The pack-insert instruction is designed as a universal operation that can perform any byte to any byte mapping through a single instruction format. By using wide load and store instructions combined with the pack-insert operation, the system achieves versatile byte mapping capabilities without requiring complex butterfly schematics or multiple control settings, simplifying the implementation while maintaining adaptability
3Productivity
If traditional pack instructions are used for interleaving operations, then data blocks can be packed, but two separate insert and pack operations are required, increasing the number of cycles
Solution Approach 1:
The patent merges two separate operations (pack and insert-extract) into a single pack-insert instruction that can perform both functions simultaneously. This eliminates the need for two separate insert and pack operations in interleaving procedures, reducing the number of execution cycles and improving the speed of interleaving operations for LTE and other 4G applications
Data Source
AI summary
A signal processing device comprising at least one control unit arranged to receive at least one pack-insert instruction, decode the received at least one pack-insert instruction, and output at least one pack-insert control signal in accordance with the received pack-insert instruction. The signal processing device further comprising at least one pack-insert component arranged to receive at least a first data block to be inserted into a sequence of data blocks to be output to at least one destination register, receive a plurality of further data blocks to be packed within the sequence of data blocks to be output to the at least one destination register, arrange the at least first data block and the plurality of further data blocks into a sequence of data blocks based at least partly on the at least one pack-insert control signal, and output the sequence of data blocks.