Electronic Device Package With Abut Portions For High Density Bumps

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Solution Overview

Problem

The miniaturization and increased complexity of semiconductor chips require more conductive bumps in electronic device packages, leading to reduced manufacturing yields and difficulties in the packaging process due to the need for smaller spaces between conductive pads.

Innovation Solution

A novel electronic device package structure featuring a semiconductor chip with a redistribution layer connected to conductive pads, an abut portion electrically contacting the redistribution layer, and a passivation layer surrounding the abut portion, which allows for reduced intervals between conductive bumps and eliminates the need for additional under-bump metallization layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If more conductive bumps are placed on the semiconductor chip to support increased functionality, then the functionality and performance of the electronic device are improved, but the space between conductive pads must be reduced making the packaging process more difficult and manufacturing yields reduced

Engineering Contradiction:
ImprovefunctionalityVSAvoidpackaging process difficulty
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent introduces a vertical dimension by forming abut portions that protrude from the first surface of the semiconductor chip through via openings in the passivation layer. This three-dimensional structure allows conductive connections to extend vertically rather than only horizontally, enabling increased bump density without proportionally reducing horizontal spacing between pads. The redistribution layer is also configured with conductive patterns that route signals through this vertical pathway, effectively utilizing the Z-axis to resolve the packaging density conflict.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If more conductive bumps are placed on the semiconductor chip to support increased functionality, then the functionality and performance of the electronic device are improved, but manufacturing yields are reduced

Engineering Contradiction:
ImprovefunctionalityVSAvoidmanufacturing yield
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The passivation layer is formed to cover the first surface of the semiconductor chip before the abut portions are formed. This preliminary protective action prevents contamination and damage to the underlying conductive patterns during subsequent packaging and bump formation processes. The via openings are precisely formed through the passivation layer to expose only the necessary portions of the redistribution layer, ensuring accurate alignment and reducing manufacturing defects that would otherwise reduce yield.

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If the space between conductive pads is reduced to increase the number of conductive bumps, then the density of conductive bumps is increased, but the packaging process becomes more difficult

Engineering Contradiction:
Improvenumber of conductive bumpsVSAvoidpackaging process difficulty
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The conductive connection structure is segmented into multiple functional components: the conductive pad structure on the second surface, the redistribution layer with conductive patterns on the first surface, and the abut portions protruding through the passivation layer. This segmentation allows each component to be optimized independently - the passivation layer provides protection and insulation, the redistribution layer routes signals, and the abut portions provide vertical connectivity - thereby simplifying the overall packaging process while maintaining high bump density.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8778798B1Electronic device package and fabrication method thereof
Publication Date: 2014.07.15 XINTEC INC
  • US8778798B1 patent drawing
  • US8778798B1 patent drawing
  • US8778798B1 patent drawing

AI summary

An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.