Semiconductor Package Adhesion Enhancer for Delamination Resistance
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Solution Overview
Problem
Semiconductor packages face challenges in achieving improved adhesion between semiconductor chips and mold layers, leading to reliability and durability issues, as well as reduced yield due to interlayer delamination.
Innovation Solution
Incorporating an adhesion enhancer layer made of acrylic polymer between the oxide layer and the mold layer, which increases the surface area and adhesion strength, preventing interlayer delamination and enhancing the reliability and durability of the semiconductor package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional semiconductor package structure without adhesion enhancer layer is used, then the device complexity is low and manufacturing is simple, but the adhesion between mold layer and chip structure is insufficient leading to interlayer delamination
Solution Approach 1:
An adhesion enhancer layer is introduced as an intermediary between the mold layer and the chip structure. This intermediate layer specifically addresses the adhesion deficiency at the interface without requiring fundamental changes to the overall package architecture, thereby improving reliability while maintaining reasonable structural complexity.
Solution Approach 2:
The adhesion enhancer layer is formed as a composite structure comprising multiple functional layers including a base layer, an adhesion promoter layer, and optionally a filler layer. This composite approach enhances adhesion strength through material composition rather than solely relying on geometric complexity.
2Reliability
If adhesion enhancer layer is added to improve adhesion, then interlayer delamination is prevented, but the manufacturing process becomes more complex
Solution Approach 1:
The adhesion enhancer layer is prepared and positioned on the chip structure before the mold layer is applied. This preliminary preparation ensures that the adhesion enhancement function is already in place before final encapsulation, preventing delamination issues that would require complex post-manufacturing repairs.
Solution Approach 2:
The adhesion enhancer layer modifies the surface properties and chemical composition at the interface between the mold layer and chip structure. By changing material parameters such as surface energy, roughness, and chemical functionality, the layer improves adhesion without requiring complex manufacturing equipment or processes.
3Productivity
If adhesion enhancer layer is incorporated, then yield is improved by preventing delamination, but the number of process steps increases
Solution Approach 1:
The formation of the adhesion enhancer layer is merged with existing manufacturing workflows where possible. For example, the adhesion promoter layer is applied during the same processing sequence as other surface preparation steps, and the filler layer formation is integrated with the molding process, thereby minimizing the increase in total process steps while still improving yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The adhesion enhancer layer effectively mitigates interlayer delamination, improving the reliability and durability of semiconductor packages and reducing process defects, thereby enhancing yield.
Implementation Method 1
an adhesion enhancer layer on an upper surface of the second chip structure, such that the adhesion enhancer layer is in contact with the mold layer
Implementation Method 2
the adhesion enhancer layer includes an acrylic polymer
Data Source
AI summary
A semiconductor package is provided. The semiconductor package includes a package substrate including bonding pads on a upper surface thereof and external connectors on a lower surface thereof, a first chip structure connected to the package substrate with a bonding wire and disposed on the package substrate, a second chip structure disposed on the package substrate and disposed next to the first chip structure, and a mold layer covering the package substrate, the first chip structure, and the second chip structure, wherein the first chip structure includes a plurality of semiconductor dies that are sequentially stacked, the second chip structure includes a second semiconductor substrate, an oxide layer on the second semiconductor substrate, and an adhesion enhancer layer disposed on the oxide layer and in contact with the mold layer, heights of the first chip structure and the second chip structure are the same.