Semiconductor Package Adhesive Layer for Uneven Chip Heights
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Solution Overview
Problem
Conventional semiconductor packages face mechanical deterioration and reliability issues due to the inability of conventional non-conductive adhesive layers to adequately receive semiconductor chips with varying heights, leading to poor bonding and void formation when a molded member is applied, especially when the difference in chip heights is significant.
Innovation Solution
A semiconductor package design featuring a non-conductive adhesive layer with varying thicknesses to accommodate chips of different heights, ensuring a firm joint between chips and the upper semiconductor chip, and using a molded member to protect the chips while minimizing void formation, with the adhesive layer's viscosity optimized to effectively receive upper portions of the chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional non-conductive adhesive layer with uniform thickness is used, then the manufacturing process is simple, but it cannot adequately receive semiconductor chips with varying heights, leading to poor bonding and void formation
Solution Approach 1:
The adhesive layer is designed with non-uniform thickness where the thickness varies according to the height of the chip stack. Specifically, the adhesive layer has a greater thickness at regions corresponding to taller chip stacks and lesser thickness at regions corresponding to shorter chip stacks, enabling each region to locally adapt to the specific chip height and achieve reliable bonding without void formation.
Solution Approach 2:
The thickness parameter of the adhesive layer is changed from a uniform value to a variable value that corresponds to the height of the chip stack. This parameter change allows the adhesive layer to accommodate chips of different heights while maintaining proper bonding and preventing void formation during molding.
2Quantity of substance
If chips of different heights are stacked to achieve high integration, then the data capacity increases, but mechanical deterioration and void formation occur due to inadequate adhesive support
Solution Approach 1:
The adhesive layer provides localized support to each chip stack according to its specific height. The non-uniform thickness distribution ensures that each chip stack receives adequate adhesive support proportional to its height, preventing mechanical deterioration and void formation while enabling high integration through stacking of multiple chips with different heights.
3Reliability
If the adhesive layer thickness is increased to accommodate taller chips, then bonding reliability improves, but void formation occurs in regions with shorter chips
Solution Approach 1:
The adhesive layer thickness is locally optimized for each chip stack height. Regions with taller chips receive greater adhesive thickness for reliable bonding, while regions with shorter chips receive lesser adhesive thickness to prevent void formation. This local quality approach eliminates the need to uniformly increase thickness across all regions.
Solution Approach 2:
Instead of uniformly applying excessive adhesive thickness to all regions (which would cause voids in shorter chip regions), the adhesive thickness is partially increased only in regions where it is needed for taller chip stacks, achieving reliable bonding without creating harmful voids in other regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances mechanical reliability and prevents degradation in package reliability by ensuring a firm bond between chips and the upper semiconductor chip, reducing void formation and maintaining package integrity even with significant differences in chip heights.
Implementation Method 1
a non-conductive adhesive layer on a lower surface of the upper chip structure and receiving upper portions of the plurality of lower chip structures
Data Source
AI summary
A semiconductor package includes a package substrate; a plurality of lower chip structures on the package substrate; an upper chip structure on the plurality of lower chip structures and covering portions of upper surfaces of the plurality of lower chip structures; a non-conductive adhesive layer on a lower surface of the upper chip structure and receiving upper portions of the plurality of lower chip structures; and a molded member on the plurality of lower chip structures and the upper chip structure.