Semiconductor Package Alignment Mark Structure for Halation-Free Bonding
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Solution Overview
Problem
Conventional semiconductor package structures face issues with alignment marks causing halation in CCD images and copper oxidation, leading to reduced accuracy in bonding semiconductor dies and warpage problems during plating processes.
Innovation Solution
A semiconductor package structure with a first passivation layer embedding a metal layer that defines a through-hole serving as an alignment mark, reducing halation and preventing copper oxidation, allowing for precise bonding and replacing the plating process with a ball drop process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a copper layer with special profile is used as an alignment mark, then the alignment mark can be formed, but the lateral side surface is not a vertical plane causing halation in CCD images
Solution Approach 1:
Instead of making the alignment mark protrude from the passivation layer (conventional approach), the invention embeds the metal layer defining the through-hole within the passivation layer, creating a recessed alignment mark structure. This inversion resolves the halation problem by eliminating the protruding lateral surfaces that cause light scattering in CCD images.
2Measurement precision
If a recess is formed by etching a passivation layer to serve as alignment mark, then alignment mark can be created, but copper is exposed to air causing oxidation
Solution Approach 1:
The metal layer is nested within the passivation layer, with the passivation layer completely covering and enclosing the metal layer. This nesting structure protects the copper from direct exposure to air, preventing oxidation while still allowing the embedded structure to serve as an effective alignment mark.
Solution Approach 2:
The passivation layer creates an inert protective environment around the metal layer, isolating the copper from oxygen in the air. This protective enclosure prevents oxidation without requiring additional inert atmosphere processing steps.
3Ease of manufacture
If a plating process is used to build bumps on the etched passivation layer, then bumps can be formed, but warpage problem occurs reducing process windows
Solution Approach 1:
The invention extracts and removes the problematic plating process from the manufacturing sequence, replacing it with a ball drop process. This elimination of the plating step removes the source of warpage issues and associated process window reductions.
Solution Approach 2:
The mechanical plating process is replaced with a ball drop process that uses controlled droplet deposition. This substitution eliminates the mechanical stress and warpage associated with plating while achieving the same functional result of forming conductive bumps.
4Device complexity
If the alignment mark is hidden by pad, then pad structure is simplified, but it becomes difficult to perform the ball drop process
Solution Approach 1:
The alignment mark structure is prepared in advance during the metal layer formation step, before pad deposition. The embedded metal layer with through-hole is created as a preliminary feature that will serve as the alignment reference for subsequent ball drop processing, ensuring alignment capability is established before manufacturing challenges arise.
Data Source
AI summary
A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.