Semiconductor Package Antenna Layout for Lower Loss and Heat
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Solution Overview
Problem
Conventional semiconductor package structures with substrate-based antennas face challenges in miniaturization, high chip-to-antenna loss, and poor thermal performance due to the thickness of the substrate and long heat-dissipation paths.
Innovation Solution
A semiconductor package structure with a conductive pattern layer formed in an insulating substrate, adjacent to one surface, and a second antenna element on the opposite surface, integrated with a redistribution layer (RDL) structure and encapsulating layer, allowing for reduced package size, improved thermal performance, and cost-effective manufacturing by using bump structures for bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a substrate-based antenna is used in conventional semiconductor packages, then wireless communication functionality is achieved, but the package size cannot be reduced due to the thick substrate requirement
Solution Approach 1:
The antenna structure transitions from a conventional planar substrate-based design to a three-dimensional configuration where antenna elements are formed on both the front surface and back surface of the insulating substrate. This dimensional change allows the antenna to achieve required performance with a thinner substrate, thereby reducing overall package size while maintaining wireless communication functionality
Solution Approach 2:
The antenna elements are nested within the insulating substrate structure, with conductive patterns embedded in or on the substrate layers. The front surface antenna element and back surface antenna element are positioned in a nested arrangement that allows compact integration, enabling the antenna system to fit within a reduced package volume while maintaining effective radiating area
2Loss of energy
If a thick substrate is used for the antenna, then antenna performance is maintained, but chip-to-antenna loss increases due to long trace length
Solution Approach 1:
By forming antenna elements on both the front and back surfaces of the substrate, the electrical connection path from the chip to the antenna is shortened. The back surface antenna element can be directly connected to chip pads through shorter vias and traces, reducing the overall trace length and minimizing resistive and inductive losses while maintaining antenna radiation performance
3Temperature
If a thick substrate is used for the antenna, then antenna structure is simplified, but thermal performance deteriorates due to long heat-dissipation path
Solution Approach 1:
The dual-surface antenna configuration allows for optimized thermal management by distributing heat generation and dissipation paths. The back surface antenna element can serve as both a radiating element and a thermal conduction path, with its conductive structure providing an additional route for heat to escape from the chip, thereby improving thermal performance without significantly increasing structural complexity
Solution Approach 2:
The back surface of the insulating substrate serves multiple functions: it provides mechanical support, enables antenna radiation through the back surface antenna element, and acts as a thermal management interface. This multi-functionality allows the same structural element to address both wireless communication and thermal dissipation requirements, improving overall device performance
Data Source
AI summary
An electronic device that has an antenna device that includes a conductive pattern layer comprising a first antenna element, the conductive pattern layer formed in an insulating substrate and adjacent to a first surface of the insulating substrate, and a second antenna element formed on a second surface of the insulating substrate opposite the first surface. The electronic device further has a semiconductor package that includes a redistribution layer (RDL) structure bonded and electrically connected to the conductive pattern layer, a first electronic component electrically connected to the RDL structure, and an encapsulating layer formed on the RDL structure and surrounding the first electronic component.