Semiconductor Package Board Grooves for Encapsulant Filling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The mismatch in thermal expansion coefficients between semiconductor chips and printed circuit boards leads to deformation in electrical connections during the fabrication process, causing reliability issues and potential malfunctioning, especially as chip size increases.
Innovation Solution
The use of a package board with solder resist featuring perimeter and extension grooves that expose circuit lines, allowing for improved encapsulant filling, which includes epoxy resin, to enhance the reliability of electrical connections and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of the semiconductor chip is increased, then the electrical connection reliability deteriorates due to thermal expansion mismatch, but the packaging capacity and performance improve
Solution Approach 1:
The patent introduces an underfill encapsulant as an intermediary substance between the chip and board. This encapsulant has thermal expansion properties that mediate between the chip and board, reducing the stress caused by thermal expansion mismatch. The encapsulant fills the gap and provides a transition zone that absorbs thermal stress, thereby maintaining electrical connection reliability even with larger chip sizes.
Solution Approach 2:
The patent modifies the gap distance parameter between the chip and board by filling it with encapsulant. This parameter change transforms the empty gap into a filled space with controlled thermal expansion properties, directly addressing the thermal mismatch issue while allowing for larger chip dimensions without compromising connection reliability.
2Reliability
If encapsulant is used to fill the gap between chip and board, then thermal conduction and mechanical strength improve, but the complexity of the fabrication process increases
Solution Approach 1:
The patent applies preliminary action by pre-forming grooves in the solder resist layer before chip mounting. These grooves are designed to guide the encapsulant flow and ensure proper filling during the underfill process. By preparing the path for encapsulant advance in advance, the process becomes more controlled and predictable, reducing fabrication complexity while maintaining the benefits of encapsulant filling.
Solution Approach 2:
The patent segments the encapsulant filling process by creating distinct regions through grooves in the solder resist. The perimeter groove and extension groove divide the filling process into controlled zones, allowing encapsulant to advance systematically. This segmentation makes the complex filling process more manageable and controllable.
3Duration of action of stationary object
If the gap between chip and board is filled with encapsulant, then the lifespan of the package increases, but the manufacturing cost increases
Solution Approach 1:
The patent employs self-service by designing the grooves in the solder resist to automatically guide the encapsulant flow during the underfill process. The encapsulant naturally follows the path of least resistance through the grooves, eliminating the need for complex external guidance mechanisms or additional processing steps. This self-guided approach reduces manufacturing complexity and cost while ensuring proper encapsulant distribution for extended package lifespan.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced encapsulant filling characteristics improve the mechanical strength and thermal conductivity of semiconductor packages, increasing their lifespan and reliability by reducing temperature differences and stabilizing connections between the chip and board.
Implementation Method 1
the encapsulant removes heat from the semiconductor chip, and provides additional thermal conduction paths which reduce the temperature difference between the semiconductor chip and the board
Implementation Method 2
an underfill method is being used of filling the gap between the board and the chip with encapsulant
Data Source
AI summary
With a semiconductor package according to an aspect of the present invention comprising a board having circuit lines, solder resist formed on a surface of the board, and a chip mounted on the board and having at least one bump attached to at least a portion of the circuit lines, where the solder resist comprises a perimeter groove, which exposes at least a portion of the circuit lines, and an extension groove, which is connected to the perimeter groove, and where encapsulant is filled in the perimeter groove and the extension groove, the filling characteristics of the encapsulant is improved for greater reliability in the electrical connections between the chip and the board.