Semiconductor Package Bond Layer Planarization After Probe Pad Damage
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving robust reliability and high yield in semiconductor packages due to issues with feature size reduction, component integration, and packaging techniques, particularly in Package-on-Package (PoP) technology.
Innovation Solution
The solution involves forming a semiconductor package with a first package component that includes an integrated circuit, through-silicon vias, and aluminum pads. The package undergoes circuit probe testing to determine known good dies, which results in recesses and protrusions on the aluminum pads. After encapsulating the pads in a dielectric bond layer, the package is processed to remove the smeared portions and reduce the height of the protrusions, improving reliability and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If circuit probe testing is performed on aluminum pads to determine known good dies, then die quality can be identified, but recesses and protrusions are formed on the pads which may cause short circuits and parasitic capacitance
Solution Approach 1:
The patent removes the harmful protrusions and smeared portions from the aluminum pads after probe testing. This extraction of the defective portions eliminates the sources of short circuits and parasitic capacitance while preserving the functional pad areas for electrical connections.
Solution Approach 2:
The patent performs planarization and protrusion removal before subsequent packaging processes. By addressing the surface defects early in the manufacturing sequence, the harmful effects are eliminated before they can cause problems in later stages, improving overall device reliability.
2Productivity
If protrusions are left on aluminum pads after probe testing, then the testing function is complete, but the protrusions create harmful effects including short circuits and increased parasitic capacitance
Solution Approach 1:
The patent converts the harmful protrusions into removable defects. By intentionally designing the process to create identifiable protrusions during testing, then systematically removing them, the harmful effect is transformed into a controlled intermediate state that can be corrected, ensuring both testing effectiveness and final device reliability.
3Ease of manufacture
If smeared portions remain on dielectric bond layer after planarization, then manufacturing process is simpler, but reliability and yield are reduced due to potential short circuits
Solution Approach 1:
The patent extracts the smeared portions from the dielectric bond layer surface through an etch process. This removal eliminates the conductive contaminants that would cause short circuits, thereby improving package yield and reliability while adding a controlled manufacturing step to ensure quality.
Data Source
AI summary
In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.