Electronic Package Buffer Layer for CTE Mismatch Warpage
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Solution Overview
Problem
Conventional electronic device packages face yield and reliability issues due to warpage caused by CTE mismatch between redistribution layers (RDLs) and encapsulation layers, which arises from differences in circuit layers and encapsulation processes.
Innovation Solution
The electronic device package includes an encapsulated electronic component with a redistribution layer (RDL) and an encapsulation layer, where a buffer layer is introduced between the substrate and the encapsulated component, and conductors are used to electrically connect the substrate to the component, with the substrate's width being smaller than the component's width to minimize warpage and improve manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple RDLs with different circuit layers are stacked and bonded to the encapsulation layer, then electrical communication among different electronic components is achieved, but warpage occurs due to CTE mismatch between RDLs and encapsulation layer
Solution Approach 1:
A buffer layer is introduced as an intermediary between the RDL and the encapsulation layer. This buffer layer has a CTE that is intermediate between the RDL and encapsulation layer, acting as a transition zone that reduces the CTE mismatch stress and prevents warpage while maintaining electrical connectivity.
Solution Approach 2:
The package structure uses a composite multi-layer configuration consisting of RDL, buffer layer, and encapsulation layer. Each layer is selected with specific material properties (particularly CTE values) to create a composite structure that balances thermal expansion characteristics and minimizes overall warpage while enabling electrical communication.
2Adaptability or versatility
If RDLs are formed both before and after die encapsulation, then flexible circuit layer integration is achieved, but manufacturing complexity and yield deterioration occur
Solution Approach 1:
The buffer layer is formed in advance on the encapsulation layer before bonding the RDL. This preliminary preparation of the buffer layer simplifies the subsequent bonding process and reduces manufacturing complexity by establishing a pre-configured interface that accommodates both pre- and post-encapsulation RDLs.
3Area of stationary object
If substrate width matches encapsulated component width, then full coverage is achieved, but warpage is exacerbated due to increased CTE mismatch area
Solution Approach 1:
The buffer layer is applied selectively at the interface region between the RDL and encapsulation layer, providing localized CTE compensation exactly where the stress concentration occurs. This targeted approach addresses the warpage issue at the critical interface without requiring full-coverage substrate extension that would exacerbate the problem.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces warpage and enhances the reliability and yield of electronic device packages by compensating for CTE mismatch and allowing for cost-effective manufacturing by bonding the circuit substrate directly to the encapsulated component instead of building up on it.
Implementation Method 1
The buffer layer is disposed between the substrate and the encapsulated electronic component and around the conductor
Data Source
AI summary
An electronic device package includes an encapsulated electronic component, a substrate, a conductor and a buffer layer. The encapsulated electronic component includes a redistribution layer (RDL) and an encapsulation layer. The first surface is closer to the RDL than the second surface is. The encapsulation layer includes a first surface, and a second surface opposite to the first surface. The substrate is disposed on the second surface of the encapsulation layer. The conductor is disposed between the substrate and the encapsulated electronic component, and electrically connecting the substrate to the encapsulated electronic component. The buffer layer is disposed between the substrate and the encapsulated electronic component and around the conductor.