Semiconductor Package Buffer Structure for TSV-Safe Die Integration
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Solution Overview
Problem
The increasing complexity of integrated circuit packages, which integrate multiple device dies with different technologies, poses challenges in manufacturing efficiency, cost, and risk of damage due to small pitches and delicate through substrate vias (TSVs).
Innovation Solution
A method involving backside thinning of semiconductor substrates, attachment to a sacrificial carrier, and subsequent processes to form a composite die, followed by encapsulation and planarization to reveal TSVs, with a buffer structure including metal vias embedded in dielectric layers, enhancing mechanical support and reducing manufacturing risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple device dies are integrated in the same package to achieve more functions, then device performance and functionality are improved, but manufacturing complexity and risk of damage increase
Solution Approach 1:
The package is divided into multiple device dies (processors, memory cubes, etc.) that can be independently manufactured and then integrated. Each die is a separate functional unit that can be processed, tested, and bonded independently, allowing complex functionality to be achieved through modular integration rather than monolithic design.
Solution Approach 2:
Multiple device dies are stacked and integrated within a single package structure, with smaller functional units nested within the larger package. The package contains multiple layers of dies connected through TSVs, creating a nested hierarchical structure that maximizes functionality within a compact volume.
2Adaptability or versatility
If small pitches and delicate through substrate vias (TSVs) are used to increase integration density, then device functionality is improved, but manufacturing precision requirements and risk of damage increase
Solution Approach 1:
TSVs are formed during the semiconductor substrate processing stage before die attachment, when the substrate is still in a robust wafer form that can support precise via formation. This preliminary formation of TSVs through the substrate allows for controlled, high-precision via creation using standard semiconductor fabrication techniques, avoiding the need to create delicate structures after the die are already assembled.
Solution Approach 2:
The TSVs are pre-formed with appropriate dimensions, spacing, and structural integrity during substrate processing, providing a cushion of manufacturing margin before the delicate die attachment and bonding steps. This beforehand preparation ensures that the precise TSV structures are already in place and protected, reducing the risk of damage during subsequent handling and assembly operations.
3Ease of manufacture
If device dies with different technologies are integrated together to form a system, then manufacturing cost is reduced, but process compatibility and manufacturing difficulty increase
Solution Approach 1:
Different device dies with different technologies are manufactured separately using their respective optimized fabrication processes, then integrated into a single package. This segmentation allows each die to be produced by specialists using the most appropriate and cost-effective processes for that particular technology, avoiding the need for a single complex multi-process fabrication line.
Solution Approach 2:
The package substrate and TSV interconnect structure serve as an intermediary that enables integration of differently-manufactured dies. The substrate provides a common platform with pre-formed TSVs that can accommodate various die types, and the bonding processes act as mediators that join disparate technologies together through standardized interfaces and interconnect structures.
Data Source
AI summary
A method includes forming a metal post over a first redistribution structure; attaching a first device die to the first redistribution structure, the first device die comprising a through via embedded in a semiconductor substrate; encapsulating the metal post and the first device die in an encapsulant, a first top surface of the encapsulant being level with a second top surface of the semiconductor substrate; recessing the second top surface to expose the through via; forming a dielectric isolation layer around the through via; forming a dielectric layer over the dielectric isolation layer; etching the dielectric layer to form a first opening and a second opening in the dielectric layer; forming a first metal via in the first opening and a second metal via in the second opening; and forming a second redistribution structure over the dielectric layer.