Package Structure Bump Layout for Stress Management
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Solution Overview
Problem
The increasing density and functionality of semiconductor dies pose manufacturing challenges due to stress caused by mismatches in the coefficient of thermal expansion (CTE) between heterogeneous materials in package structures, leading to potential damage from stress concentration.
Innovation Solution
A package structure design that includes a redistribution structure with bumps spaced apart from the chip edge and a keep-out zone to misalign underlying and overlying stresses, distributing stress and preventing damage to the redistribution structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the density of I/O pads is increased to integrate more functions into smaller semiconductor dies, then the functionality and integration density are improved, but the manufacturing difficulty and stress concentration increase
Solution Approach 1:
The patent implements fan-out chip packaging that redistributes I/O pads from the die surface to a larger area on the package substrate, effectively moving the I/O pad layout from two-dimensional die constraints to a three-dimensional package-level arrangement. This dimensional transition allows higher I/O density without increasing die size or manufacturing complexity
Solution Approach 2:
The patent introduces a package substrate as an intermediary between the semiconductor die and the external environment. This substrate acts as a stress buffer that decouples the thermal expansion mismatch between the die and surrounding materials, reducing stress concentration on the high-density I/O pads while enabling their redistribution to a larger area
2Adaptability or versatility
If heterogeneous materials with different CTE values are used in the package structure, then the functionality and performance are improved, but stress concentration and potential damage occur
Solution Approach 1:
The package substrate serves as a stress-buffering intermediary between heterogeneous materials with different CTE values. By positioning this compliant substrate between the rigid die and other package components, the design decouples thermal expansion mismatches, preventing stress concentration at critical interfaces while maintaining the functional benefits of material heterogeneity
Solution Approach 2:
The patent modifies the mechanical parameter profile of the package structure by introducing materials with intermediate CTE values and varying thicknesses. This gradient approach changes the stress distribution parameters throughout the package, transforming concentrated stress points into distributed stress fields that prevent damage to high-density I/O regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability of the package structure by mitigating stress concentration and preventing damage, ensuring the integrity of the redistribution structure and overall package reliability.
Implementation Method 1
A package structure design that includes a redistribution structure with bumps spaced apart from the chip edge and a keep-out zone to misalign underlying and overlying stresses, distributing stress and preventing damage to the redistribution structure
Data Source
AI summary
A package structure is provided. The package structure includes a molding layer and a first chip having a first corner and a second corner and a second chip having a third corner and a fourth corner embedded in the molding layer. The package structure also includes first bumps electrically connected to the first chip without overlapping the first chip and the second chip. In addition, the first corner and the second corner of the first chip and the third corner and the fourth corner of the second chip form a first region in a top view, and no bump overlaps the first region.