Semiconductor Package Capping Layer for Thermal Stress Relief
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Interfaces between a fan-out wafer level package (FOWLP) and an underfill material portion experience mechanical stress during assembly and use, leading to cracks in the underfill material and other package components, which can induce additional cracks in semiconductor dies and solder material portions.
Innovation Solution
A capping layer is formed over the semiconductor package structure to mitigate thermally-induced stress and strain, reducing deformation and mechanical degradation by covering surfaces of semiconductor dies, molding compound die frames, and interposers, which can be made of materials like stainless steel, copper, nickel, tungsten, aluminum, magnesium, titanium, and gold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a FOWLP assembly is subjected to mechanical stress during handling and attachment, then the assembly can be processed and mounted, but cracks form in the underfill material and package components
Solution Approach 1:
A capping layer is formed over the FOWLP assembly before it undergoes mechanical stress during handling and attachment. This capping layer acts as a cushioning protective structure that absorbs and distributes mechanical stress, preventing stress concentration at the interfaces between the FOWLP and underfill material. By providing this protective barrier in advance, the capping layer prevents crack formation in the underfill material while still allowing the assembly to be handled and mounted.
2Adaptability or versatility
If the FOWLP assembly undergoes mechanical shock during use, then the device can be operated, but additional cracks are induced in semiconductor dies and solder material portions
Solution Approach 1:
The capping layer functions as a counterweight structure that opposes and balances mechanical shock forces during device operation. When mechanical shock occurs, the capping layer provides a counteracting force that distributes the shock load across the entire FOWLP assembly, preventing localized stress concentration that would otherwise induce additional cracks in semiconductor dies and solder material portions. This allows the device to operate normally while gaining enhanced shock resistance.
3Adaptability or versatility
If interfaces between FOWLP and underfill material are subjected to thermal stress, then the assembly can function, but delamination occurs reducing reliability
Solution Approach 1:
The capping layer modifies the thermal stress parameters at the FOWLP-underfill material interfaces by providing an additional thermal expansion buffer. The capping layer's thermal expansion characteristics are designed to compensate for differential thermal expansion between the FOWLP and underfill material, thereby reducing thermal stress concentration at the interfaces. This maintains interface bonding integrity while allowing the assembly to function across varying temperature conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The capping layer effectively reduces the formation of cracks and delamination, enhancing the reliability of the interposer and package substrate by counteracting thermally-induced mechanical stress.
Implementation Method 1
A capping layer is formed over the semiconductor package structure to mitigate thermally-induced stress and strain
Data Source
AI summary
A disclosed semiconductor structure may include an interposer, a first semiconductor die electrically coupled to the interposer, a packaging substrate electrically coupled to the interposer, and a capping layer covering one or more of a first surface of the first semiconductor die and a second surface of the packaging substrate. The capping layer may be formed over respective surfaces of each of the first semiconductor die and the packaging substrate. In certain embodiments, the capping layer may be formed only on the first surface of the first semiconductor die and not formed over the package substrate. In further embodiments, the semiconductor structure may include a second semiconductor die, such that the capping layer covers a surface of only one of the first semiconductor die and the second semiconductor die. The semiconductor structure may include a molding compound die frame that is partially or completely covered by the capping layer.