Package Carrier Segmented Conductive Vias for Compact Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As chip packages shrink, the complexity and cost of packaging processes increase due to closely spaced interconnections in package carriers, which require improved electrical properties, reduced size, and increased I/O ports while maintaining reliability and structural integrity.
Innovation Solution
A package carrier design featuring a dielectric layer with conductive vias of varying diameters and a patterned etching stop layer, enhancing structural rigidity and reliability by creating a locking mechanism for conductive posts within the dielectric layer, and allowing for efficient stress compensation and improved coupling between conductive patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If chip packages are reduced in size, then compactness is improved, but interconnections become smaller and more closely spaced increasing complexity and cost
Solution Approach 1:
The conductive via is segmented into multiple sections: a first conductive section extending from the first surface to a first depth, and a second conductive section extending from the first surface to a second depth greater than the first depth. This segmentation allows each section to serve different functional purposes, enabling the via to maintain electrical connectivity while accommodating varying spacing requirements and reducing overall via diameter in certain regions, thereby reducing package size without proportionally increasing complexity
Solution Approach 2:
Different portions of the conductive via have different properties: the first conductive section has a larger lateral dimension providing robust connectivity at the chip interface, while the second conductive section has a smaller lateral dimension allowing closer spacing between adjacent vias. This local variation in quality enables the package to achieve both reliable electrical connections and reduced overall size with controlled complexity
2Volume of moving object
If interconnections are made smaller and more closely spaced, then package size is reduced, but manufacturing cost and complexity increase
Solution Approach 1:
The conductive via is divided into segments with different lateral dimensions, allowing the manufacturing process to use larger, easier-to-manufacture sections where robust connectivity is needed while using smaller sections only where absolutely necessary for size reduction, thereby maintaining ease of manufacture while achieving compactness
Solution Approach 2:
The first conductive section is formed first, establishing a robust foundation for electrical connectivity. Subsequently, the second conductive section is formed to extend deeper into the substrate. This preliminary action of forming the larger section first simplifies the manufacturing process by establishing connectivity before requiring the more complex smaller section
Data Source
AI summary
A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments.