Semiconductor Package Carrier Layout With Single-Sided Etching
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Solution Overview
Problem
Conventional lead frame package carrier structures face challenges in controlling etching depth and side etching, leading to inconsistent electrical quality, unstable yield, and limited flexibility in product design, particularly in multi-chip packaging.
Innovation Solution
A semiconductor package carrier structure utilizing single-sided etching and electroplating processes to define conductive pillars and die placement portions with concave arcs, combined with a patterned circuit layer, enhancing electrical connections and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If double-sided half etching process is used to form the substrate structure, then the routing capability is improved, but the etching depth and side etching are difficult to control, resulting in poor consistency and unstable yield
Solution Approach 1:
The patent divides the substrate structure into distinct regions: a first region with through-holes penetrating both first and second surfaces, and a second region with only a first surface exposed. This segmentation allows different surface treatments and electrical connections for different functional areas, improving routing capability while maintaining precise control over etching depth through single-sided etching processes.
2Adaptability or versatility
If double-sided half etching process is used, then the routing capability is improved, but the consistency of the lead frame package carrier structure deteriorates
Solution Approach 1:
The substrate is segmented into regions with different hole configurations (through-holes vs. non-through holes), allowing consistent single-sided etching while achieving diverse routing capabilities. This ensures uniform etching depth control across all substrates, improving consistency.
Solution Approach 2:
Different regions of the substrate have different properties: some areas have through-holes for vertical routing, while other areas have non-through holes for surface-level routing. This local differentiation enables versatile routing while maintaining overall structural consistency through standardized single-sided etching processes.
3Adaptability or versatility
If double-sided half etching process is used, then the routing capability is improved, but the yield becomes unstable
Solution Approach 1:
By segmenting the substrate into regions with different hole types and implementing single-sided etching, the patent achieves precise control over material removal. This reduces variability in the manufacturing process, leading to more stable yield while maintaining the ability to provide diverse routing options.
4Manufacturing precision
If single-sided etching is used to form the substrate structure, then the manufacturing precision is improved, but the routing capability deteriorates
Solution Approach 1:
The patent compensates for the limitations of single-sided etching by creating local variations in the substrate structure. Through-holes provide vertical routing paths, while non-through holes enable surface-level routing, all achieved with precise single-sided etching control. This local differentiation maintains versatile routing capability while ensuring high manufacturing precision.
Solution Approach 2:
The patent utilizes both vertical (through-holes penetrating the substrate) and horizontal (surface-level routing around non-through holes) dimensions to provide versatile routing capability. This multi-dimensional approach to routing is achieved through precise single-sided etching that creates different hole types in different regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves yield and design flexibility by stabilizing electrical quality and enabling multi-chip packaging, addressing the inconsistencies of double-sided etched structures.
Implementation Method 1
the substrate body has a plurality of openings penetrating through the substrate body to define at least one die placement portion and a plurality of conductive pillars distributed around the die placement portion, wherein side surfaces of the die placement portion and the plurality of conductive pillars are in a concave arc shape
Implementation Method 2
A semiconductor package carrier structure utilizing single-sided etching and electroplating processes to define conductive pillars and die placement portions with concave arcs, combined with a patterned circuit layer
Data Source
AI summary
A semiconductor package carrier structure is provided and includes a substrate body, a dielectric material, and a patterned circuit layer. The substrate body has a plurality of openings, a plurality of conductive pillars, and at least one die placement portion. The dielectric material is disposed in the plurality of openings. The patterned circuit layer is disposed on a surface of the substrate body. Side surfaces of the plurality of conductive pillars and the die placement portion are all in a concave arc shape. The patterned circuit layer includes a die placement pad corresponding to the die placement portion and a plurality of bonding pads corresponding to the plurality of conductive pillars. A method of manufacturing the semiconductor package carrier structure is further provided.