Package Carrier Thickness Reduction via Core Dielectric Extraction
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Solution Overview
Problem
Conventional chip packaging methods rely heavily on a core dielectric layer, making it difficult to reduce the thickness of the package carrier and thus the chip package, which limits miniaturization efforts.
Innovation Solution
A manufacturing method that forms a package carrier by using a supporting board with a patterned circuit layer, an insulating layer, and conductive connection structures, where the patterned circuit layer is embedded within the insulating layer, allowing for the removal of the supporting board to achieve a thinner package structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a core dielectric layer is used as the core material in the package carrier, then the structural stability and electrical insulation are improved, but the thickness of the package carrier increases significantly
Solution Approach 1:
The patent removes the core dielectric layer from the package carrier structure entirely. Instead of using a traditional core dielectric layer as the foundation, the invention uses only thin insulating layers that are deposited directly on the substrate, extracting the essential insulation function while eliminating the thickness burden of a bulky core dielectric layer.
Solution Approach 2:
The patent employs thin film insulating layers deposited through semiconductor manufacturing processes to replace the thick core dielectric layer. These thin films provide the necessary electrical insulation and structural support with minimal thickness, enabling the package carrier to achieve both reliability and compactness.
2Reliability
If a core dielectric layer is used as the core material, then the electrical insulation performance is improved, but the overall package thickness increases
Solution Approach 1:
The invention extracts the electrical insulation function from the bulky core dielectric layer and implements it through thin insulating layers deposited directly on the substrate. This separation of function from form allows achieving adequate insulation performance without the thickness penalty of a traditional core dielectric layer.
Solution Approach 2:
The patent changes the thickness parameter of the insulating layers from the conventional thick core dielectric layer to thin film dimensions. By controlling the deposition thickness through semiconductor manufacturing processes, the invention achieves the minimum required insulation performance while minimizing the overall package thickness.
3Manufacturing precision
If conventional additive or subtractive processes are used to form the package carrier, then the circuit patterns are formed accurately, but the core dielectric layer thickness cannot be reduced
Solution Approach 1:
The patent removes the core dielectric layer from the manufacturing process entirely. Instead of forming circuit patterns on top of a thick core dielectric layer, the invention deposits thin insulating layers directly on the substrate and forms circuit patterns within or on these thin layers, eliminating the thickness constraint while maintaining manufacturing precision through standard semiconductor processes.
Solution Approach 2:
The invention transitions from a three-dimensional structure with a thick core dielectric layer to a more planar, two-dimensional structure where circuit patterns are formed within thin insulating layers. This dimensional change allows maintaining pattern accuracy while dramatically reducing the vertical thickness of the package carrier.
Data Source
AI summary
A manufacturing method of a package carrier is provided. A supporting board having an upper surface which a patterned circuit layer formed thereon is provided. A portion of the upper surface is exposed by the patterned circuit layer. An insulating layer and a conducting layer located at a first surface of the insulating layer are laminated onto the patterned circuit layer. The patterned circuit layer and the exposed portion of the upper surface are covered by the insulating layer. Plural conductive connection structures are formed on the patterned circuit layer. Plural of pads respectively connecting the conductive connection structures and exposing a portion of the first surface of the insulating layer is defined by patterning the conductive layer. The supporting board is removed so as to expose a second surface of the insulating layer. The second surface and a bonding surface of the patterned circuit layer are coplanar.