Semiconductor Package Cavity Interconnect to Reduce FPC Warpage
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Solution Overview
Problem
Existing electronic assemblies using flexible printed circuits (FPCs) face challenges with increased package size due to joint areas required for soldering and warpage issues that affect yield and reliability.
Innovation Solution
The electronic assembly incorporates a protection layer with a cavity to accommodate a conductive element, eliminating the need for joint areas and reducing warpage by providing a secure and flexible connection between substrates, allowing for improved layout design and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hot bar reflow soldering is used to bond FPC to substrates, then electrical interconnection is achieved, but package size increases due to required joint areas
Solution Approach 1:
The patent extracts the bonding function from traditional soldering joints and relocates it to the cavity structure. The conductive element is inserted into a cavity formed in the protection layer, eliminating the need for external joint areas on substrates while maintaining electrical connectivity.
Solution Approach 2:
The patent transitions from planar joint areas on substrate surfaces to a three-dimensional cavity structure within the protection layer. This vertical dimensionality change allows electrical connection without consuming horizontal package area.
2Adaptability or versatility
If FPC is used for connecting structures, then signal transmission in bending directions is enabled, but warpage occurs affecting yield
Solution Approach 1:
The patent employs a flexible protection layer that can accommodate the conductive element without requiring rigid substrate joint areas. This flexible structure enables signal transmission while controlling warpage through the cavity design that accommodates dimensional changes.
3Reliability
If joint areas are required on substrates for bonding, then electrical connection is established, but layout flexibility is reduced
Solution Approach 1:
The patent segments the electrical connection function from the substrate surface to the protection layer cavity. This separation allows independent optimization of substrate layout and connection points, enhancing layout flexibility while maintaining reliable electrical connection.
Data Source
AI summary
The present disclosure provides an electronic assembly including a semiconductor device package. The semiconductor device package includes a first package and a conductive element. The first package includes an electronic component and a protection layer covering the electronic component. The conductive element is supported by the protection layer and electrically connected with the electronic component through an electrical contact. A method for manufacturing a semiconductor device package is also provided in the present disclosure.


